대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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BIST 환경에서의 천이 억제 스캔 셀 구조

Transition Repression Architecture for scan CEll (TRACE) in a BIST environment

  • 김인철 (연세대학교 전기전자공학과) ;
  • 송동섭 (연세대학교 전기전자공학과) ;
  • 김유빈 (연세대학교 전기전자공학과) ;
  • 김기철 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Kim In-Cheol (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Song Dong-Sup (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim You-Bean (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim Ki-Cheol (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
  • 발행 : 2006.06.01
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초록

본 논문은 테스트 수행 중 발생하는 전력 소모를 줄이기 위한 변경된 스캔 셀 구조를 제안하고 있다. 이는 스캔 이동 중에 조합 회로 부분에서 발생하는 천이를 억제할 뿐 아니라 동시에 스캔 체인 내에서 발생하는 천이도 감소시킨다. 뿐만 아니라 캡쳐 싸이클에서 발생하는 천이 또한 제한시킨다. 제안하는 방식은 test-per-scan BIST 구조에 적합하고 싱글 스캔 구조 뿐 아니라 멀티 스캔 구조에도 적응 가능하다. 실험 결과는 제안하는 방법이 기존의 방법들과 비슷한 수준의 고장 검출율을 가지면서 보다 적은 전력을 소모한다는 것을 보여준다.

This paper presents a modified scan cell architecture to reduce the power dissipation during testing. It not only eliminates switching activities in the combinational logic during scan shifting but also reduces switching activities in the scan chain during the time. Furthermore, it limits the transitions on capture cycles. It can be made for test-per-scan BIST and employed in both single scan style and multiple scan style. Experimental results demonstrate that the proposed structure achieves the same fault coverage with lower power consumption compared to other existing BIST schemes.

키워드

참고문헌

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