3 Dimensional Packaging Technology Using Via

Via를 이용한 3차원 패키징 기술

  • Published : 2006.04.01

Abstract

Keywords

References

  1. 홍성준, 이영우, 김규석, 이기주, 김정오, 박지호, 정재필, '3차원 실장을 위한 Si-wafer의 via hole 딥핑 충전'. 대한용접학회 춘계 학술대회. 2006년 5월
  2. Gao J.X., Yeo L.P., Chan-Park M.B., Miao J.M., Yan Y.H., Sun J.B., Lam Y.C. and Yue C.Y., 'Antistick postpassivation of high-aspect ratio silicon molds fabricated by deep-reactive ion etching'. Jounal of microelectromechanical systems. 15-1. 2006
  3. NT Nguyen . KT Ng. E. Boellaard. NP Pham . G. Craciun, PM Sarro. and. JN Burghartz. 'ThroughWafer Copper Electroplating for RF Silicon Technology'. ESSDERC 2002
  4. Yamamoto S., Itoi, K., Suemasu. T. and Takizawa, T, 'Si through-hole interconnections filled with Au-Sri solder by molten metal suction method' , IEEE Transaction on 19-23 (2003), 642 - 645
  5. Takizawa T., Yamamoto S., Itoi. K. and Suemasu, T., 'Conductive interconnections through thick silicon substrates for 3D packaging', IEEE Transaction on 20-24 (2002), 388 - 391
  6. Noda screen Co., Ltd. 'Introduction to Yuutei(laser via) plug processing'. Sep. 2002
  7. Okuno A.. Fujita N., 'Filling the via hole of IC by VPES (Vacuum Printing Encapsulation Systems) for stacked chip (3D packaging)', IEEE Transaction on 28-31 (2002).1444-1448
  8. Seok Won Jung. Jae Pil .Jung, and Y(Norman) Zhou, 'Characteristics of Sn-Cu Solder Bump Formed by Electroplating for Flip Chip', IEEE Transactions on Electronics Packaging Manufacturing. 29-1 (2006). 10-16 https://doi.org/10.1109/TEPM.2005.863266
  9. Hara K., Kurashima Y. Hashimoto N., Matsui K., Matsuo Y., Miyazawa I.. Kobayashi T., Yokoyama Y. and Fukazawa M., 'Optimization for Chip Stack in 3-D Packaging', IEEE Transaction on Volume 28. Issue 3. 2005, 367-376