The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Design and Implementation of HomePNA 2.0 MAC Controller Circuit

HomePNA 2.0 MAC Controller 회로의 설계 및 구현

  • 김종원 (한국전자통신연구원 센서네트워킹연구팀) ;
  • 김대영 (충남대학교 공과대학장)
  • Published : 2006.01.01
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Abstract

The Home Phoneline Networking Alliance(HomePNA) 2.0 technology can establish a home network using existing in-home phone lines, which provides a channel rate of 4-32 Mbps. HomePNA 2.0 Medium Access Control(MAC) protocol adopts an IEEE 802.3 Carrier Sense Multiple Access with Collision Detection(CSMA/CD) access method, Quality of Service(QoS) algorithm, and Distributed Fair Priority Queuing(DFPQ) collision resolution algorithm. In this paper, we describe some performance analysis results of HomePNA 2.0 MAC protocol and the requirements of HomePNA 2.0 MAC controller. Then, we propose the architecture of HomePNA 2.0 MAC controller circuit, show the simulation result of each block included in HomePNA 2.0 MAC controller, and present the HomePNA 2.0 transceiver chip that we have implemented.

Home Phoneline Networking Alliance(HomePNA) 2.0 기술은 기존의 댁내 전화 선로를 사용하여 홈 네트워크를 구축하는 기술로서, 4-32 Mbps의 고속 데이터 전송 속도를 제공한다. 이러한 HomePNA 2.0의 Medium Access Control(MAC) 프로토콜은 IEEE 802.3 Carrier Sense Multiple Access with Collision Detection(CSMA/CD) 방식을 사용하면서, Quality of Service(QoS) 알고리즘을 제공하고, 충돌 해결 알고리즘은 Distributed Fair Priority Queuing(DFPQ) 알고리즘을 사용한다. 본 논문은 HomePNA 2.0 MAC 프로토콜의 성능 분석 결과와 HomePNA 2.0 MAC Controller의 요구 사항을 기술하고, 우리가 설계한 HomePNA 2.0 MAC Controller 회로의 구조를 제시하며, HomePNA 2.0 MAC Controller를 구성하는 각 블록의 모의 실험 결과를 제공하고, 우리가 구현한 HomePNA 2.0 Transceiver 칩을 제시한다.

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References

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