대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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초광대역 통신시스템 응용을 위한 이중채널 6b 1GS/s 0.18um CMOS ADC

A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems

  • 발행 : 2006.12.25
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 초광대역 통신시스템 응용을 위한 이중채널 6b 1GS/s A/D 변환기 (ADC)를 제안한다. 제안하는 ADC는 IGS/s의 신호처리속도에서 전력, 칩 면적 및 정확도를 최적화하기 위해 인터폴레이션 기반의 6b 플래시 ADC 회로로 구성되며, 입력 단에 광대역 열린 루프 구조의 트랙-앤-홀드 증폭기를 사용하였으며, 넓은 입력신호범위를 처리하기 위한 이중입력의 차동증폭기와 함께 래치 단에서의 통상적인 킥-백 잡음 최소화기법 등을 적용한 비교기를 제안하였다. 또한, CMOS 기준 전류 및 전압 발생기를 온-칩으로 집적하였으며, 디지털 출력에서는 새로운 버블 오차 교정회로를 제안하였다. 본 논문에서 제안하는 ADC는 0.18um 1P6M CMOS 공정으로 제작되었으며, 1GS/s의 동작속도에서 SNDR 및 SFDR은 각각 최대 30dB, 39dB를 보이며, 측정된 시제품 ADC의 DNL 및 INL은 각각 1.0LSB, 1.3LSB 수준을 보여준다. 제안하는 이중채널 ADC의 칩 면적은 $4.0mm^2$이며, 측정된 소모 전력은 1.8V 전원 전압 및 1GS/s 동작속도에서 594mW이다.

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

키워드

참고문헌

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