대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

새로운 Worstcase 최적화 방법 및 공정 편차를 고려한 배선의 Worstcase 설계 환경

New Worstcase Optimization Method and Process-Variation-Aware Interconnect Worstcase Design Environment

  • 발행 : 2006.10.25
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

급격한 공정 기술의 발전과 새로운 소재의 도입은 공정 제어를 어렵게 할 뿐만 아니라, 공정 편차를 증가시킨다. 이러한 공정 편차는 레이아웃상의 데이타와 실제 웨이퍼 상의 데이타간의 차이를 유발시킴으로써, 설계자가 원하는 성능을 갖는 회로를 구현하는데 많은 장애가 되고 있다. 따라서, 본 논문은 공정 편차가 회로의 특성에 미치는 영향을 $0.13{\mu}m$ 이하의 설계에 반영 할 수 있도록 배선의 worstcase를 정확하고 빠르게 결정할 수 있는 새로운 설계 환경을 구현하였다. 이를 위하여 Common Geometry와 Maximum Probability 기법을 개발하였으며, 이들을 기반으로 새로운 worstcase 최적화 알고리즘을 제안하였다. 본 논문께서 제안된 알고리즘의 정확성 검증은 UMC $0.13{\mu}m$ Logic 공정을 사용하여 제작된 31단 Ring Oscillator의 시간 지연(Delay time)을 측정값과 비교하였다. 검증 결과, 제안된 알고리즘을 사용하여 worstcase 최적화를 할 경우, 신호선 위에 도선이 있는 경우와 없는 경우 모두 상대 오차가 1.0% 내외로 기존의 optimizer를 사용한 경우에 비하여 두배이상 정확함을 알 수 있었다. 또한, 새로운 worstcase 설계 환경을 사용하여 최적화한 경우, 기존의 optimizer를 사용하여 최적화한 경우에 비하여 worstcase 최적화 속도가 약 32.01% 단축되었음을 확인하였다. 더불어, 기존의 방법으로 정확한 시뮬레이션이 어려웠던 비정규분포를 갖는 경우에 대해서도 정확한 worstcase를 예측함을 확인하였다.

The rapid development of process technology and the introduction of new materials not only make it difficult for process control but also as a result increase process variations. These process variations are barriers to successful implementation of design circuits because there are disparities between data on layout and that on wafer. This paper proposes a new design environment to determine the interconnect worstcase with accuracy and speed so that the interconnect effects due to process-induced variations can be applied to designs of $0.13{\mu}m$ and below. Common Geometry and Maximum Probability methods have been developed and integrated into the new worstcase optimization algorithm. The delay time of the 31-stage Ring Oscillator, manufactured in UMC $0.13{\mu}m$ Logic, was measured, and the results proved the accuracy of the algorithm. When the algorithm was used to optimize worstcase determination, the relative error was less than 1.00%, two times more accurate than the conventional methods. Furthermore, the new worstcase design environment improved optimization speed by 32.01% compared to that of conventional worstcase optimizers. Moreover, the new worstcitse design environment accurately predicted the worstcase of non-normal distribution which conventional methods cannot do well.

키워드

참고문헌

  1. International Technology Roadmap for Semiconductors. 2005 Edition, available online. http://www.itrs.net/Common/2005ITRS/Home2005.htm
  2. N. Nagaraj, T. Bonifield, A. Singh, F. Cano, U. Narasimha, M. Kulkarni, P. Balsara, and C. Cantrell, 'Benchmarks for interconnect parasitic resistance and capacitance,' Proc. of ISQED, pp. 163-168, March 2003 https://doi.org/10.1109/ISQED.2003.1194726
  3. J. Joyner, P. Zarkesh-Ha, and J. Meindl, 'A global interconnect design window for a three-dimensional system-on-a-chip,' Proc. of the IEEE 2001 lITC, pp. 154 -156, June 2001 https://doi.org/10.1109/IITC.2001.930044
  4. V. Mehrotra and D. Boning, 'Technology scaling impact of variation on clock skew and interconnect delay,' Proc. of the IEEE 2001 lITC, pp. 122-124, June 2001 https://doi.org/10.1109/IITC.2001.930035
  5. Y. Liu, S.R. Nassif, L.T. Pileggi, and A.J. Strojwas, 'Impact of interconnect variations on the clock skew of a gigahertz microprocessor,' Proc. of Design Automation Conference, pp.168-171, June 2000
  6. K Takeuchi, K. Yanagisawa, T. Sato, K. Sakamoto, and S. Hojo, 'Probabilistic crosstalk delay estimation for asics,' IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1377-1383, September 2004 https://doi.org/10.1109/TCAD.2004.833605
  7. P. Zarkesh-Ha, S. Lakshrninarayann, K. Doniger, W. Loh, and P. Wright, 'Impact of interconnect pattern density information on a 90nm technology asic design flow,' Proc. of ISQED, pp. 405-409, March 2003 https://doi.org/10.1109/ISQED.2003.1194767
  8. A. Teene, B. Davis, R. Castagnetti, J. Brown, and S. Ramesh, 'Impact of interconnect process variations on memory performance and design,' Proc. of ISQED, pp. 694-699, March 2005 https://doi.org/10.1109/ISQED.2005.63
  9. O.S. Nakagawa, N. Chang, S. Lin, and D. Sylvester, 'Circuit impact and skew-corner analysis of stochastic process variation in global interconnect,' Proc. of International Interconnect Technology Conference, pp. 230-232, May 1999 https://doi.org/10.1109/IITC.1999.787130
  10. Y. Cao and L.T. Clark, 'Mapping statistical process variations toward circuit performance variability: analytical modeling approach,' Proc. of Design Automation Conference, pp. 658-663, June 2005
  11. E. Matoglu, M. Swaminathan, N. Pham, D. Araujo, and M. Cases, 'Statistical signal integrity analysis and diagnosis methodology for high-speed systems,' IEEE Trans on Advanced Packaging, vol.27, no.4, pp.611 - 629, November 2004 https://doi.org/10.1109/TADVP.2004.831856
  12. W.Y. Jung, S.Y. Oh, J.T. Kong, and K.H. Lee, 'Interconnect modeling in deep-submicron design,' IEICE Trans. on Electronics, vol. E83-C, no. 8, pp. 1311-1316, August 2001
  13. A. Agarwal, V. Zolotov, and D. Blaauw, 'Statistical clock skew analysis considering intradie-process variations,' IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 23, no. 8, pp. 1231-1242, August 2004 https://doi.org/10.1109/TCAD.2004.831573
  14. Y. Xu, K. L. Hsiung, X. Li, I. Nausieda, S. Boyd, and L.T. Pileggi, 'OPERA: optimization with ellipsoidal uncertainty for robust analog IC design,' Proc. of Design Automation Conference, pp. 632-637, June 2005
  15. W.Y. Jung, S.Y. Oh, K.H. Lee, and J.T. Kong, 'Interconnect modeling in dsm design using a statistically-based worstcase interconnect model generator SWIM),' Proc. on DATE, pp. 113-116, March 2000
  16. W.Y. Jung, H. Kim, K.H. Sea, and J.K. Wee, 'The statistical interconnect worst-case corner determination with maximum probability,' Proc. on Korean Conference on Semiconductors, pp. February 2006
  17. D. Boning, 'Layout practice impact on timing and yield,' Tutorial, ISQED, San Jose CA, March 2003
  18. UMC 0.13um 1P8M Logic Cu BEOL Process with FSG Dielectric Process Interconnect Capacitance Model (Rev. 0.2), UMC, SPEC No:G-04-LOGICI3-IP8M-CU_FSG-INTERCAP 07.07.2003