References
- P. Villarrubia, 'Important Placement Considerations for Modem VLSI Chips,' Proc. of ISPD, pp.6, 2003
- C. Sechen and A. Sangiovanni-Vincentelli, 'TimberWolf3.2: A New Standard Cell Placement and Global Routing Package,' Proc. of the DAC, pp.432-439, 1986
- M. Sarrafzadeh and M. Wang, 'NRG: global and detailed placement,' Proc. of ICCAD, pp.532-537, 1997
- C. Sechen and K. W. Lee, 'An Improved Simulated Annealing Algorithm for Row-Based Placement,' Proc. of ICCAD, pp. 478-481, 1987
- X. Yang, M. Wang, K. Eguro, and M. Sarrafzadeh, 'A snap-on placement tool,' Proc. of ISPC, pp.153-158, 2000 https://doi.org/10.1145/332357.332392
- A. E. Caldwell, A. B. Kahng, and Igor L. Markov, 'Can Recursive Bisection Alone Produce Routable Placements?,' Proc. of DAC, pp.477-482, 2000 https://doi.org/10.1145/337292.337549
- D. J.-H, Huang, and A. B. Kahng, 'Partitioning-Based Standard-Cell Global Placement with an Exact Objective,' Proc. of ISPD, pp.18-25, 1997 https://doi.org/10.1145/267665.267674
- M. C. Yildiz and P. H. Madden, 'Improved Cut Sequences for Partitioning Based Placement,' Proc. of DAC, pp.776-779, 2001 https://doi.org/10.1145/378239.379064
- Ke Zhong, and Shantanu Dutt, 'Effective Partition-Driven Placement with Simultaneous Level Processing and Global Net Views,' Proc. of ICCAD, pp. 254-259, 2000 https://doi.org/10.1109/ICCAD.2000.896482
- Jason Cong, Michail Romesis, and Min Xie, 'Optimality, Scalability, and Stability Study of Partitioning and Placement Algorithms,' Proc. of ISPD, pp.88-94, 2003 https://doi.org/10.1145/640000.640021
- A. E. Caldwell, A. B. Kahng, and I. L. Markov, 'Optimal Partitioners and End-Case Placers for Standard-Cell Layout,' Proc. of ISPD, pp. 90-96, 1999 https://doi.org/10.1145/299996.300032
- B. W. Kernighan, and S. Lin, 'An Efficient Heuristic Procedure for Partitioning Graphs,' Bell Syst. Tech., vol.49, no.2, pp.291-308, 1970 https://doi.org/10.1002/j.1538-7305.1970.tb01770.x
- C. M. Fiduccia and R. M. Mattheyses, 'A Linear-Time Heuristic for Improving Network Partitions,' Proc, of DAC, pp. 175-181, 1982
- H. Eisenmann and F. M. Johannes, 'Generic Global Placement and Floorplanning,' Proc. of DAC, pp.269-274, 1998 https://doi.org/10.1145/277044.277119
- Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin, 'Timing Driven Force Directed Placement with Physical Net Constraints,' Proc. of ISPD, pp. 60-66, 2003 https://doi.org/10.1145/640000.640016
- N. Viswanathan and Chris C. Chu, 'FastPlace: Efficient Analytical Placement Using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model,' IEEE Trans. CAD of Integrated Circuits and Systems, vol.24, no.5, pp.722-733, 2005 https://doi.org/10.1109/TCAD.2005.846365
- S. Goto, 'An Efficient Algorithm for the Two-Dimensional Placement Problem m Electrical Circuit Layout,' IEEE Trans. on Circuits and Systems, vol.28-1, pp.12-18, 1981
- P. N. Parakh, R. B. Brown, and K. A. Sakallah, 'Congestion Driven Quadratic Placement,' Proc. of the 35th DAC, pp. 275-278, 1998 https://doi.org/10.1145/277044.277121
- X. Yang, B.-K. Choi, and M. Sarrafzadeh, 'Routability Driven White Space Allocation for Ffixed-Die Standard-Cell Placement,' Proc. of ISPD, pp.42-47, 2002
- H. Etawil, S. Areibi, and A. Vannelli, 'Attractor-Repeller Approach for Global Placement,' Proc. of ICCAD, pp.20-24, 1999 https://doi.org/10.1109/ICCAD.1999.810613
- M. Wang, X. Yang, and M. Sarrafzadeh, 'Dragon2000: Standard-Cell Placement Tool for Large Industry Circuits,' Proc. of ICCAD, pp.260-263, 2000 https://doi.org/10.1109/ICCAD.2000.896483
- X. Yang, B.-K. Choi and M. Sarrafzadeh, 'A Standard-Cell Placement Tool for Designs with High Row Utilization,' Proc. of the 2002 IEEE International Conference on Computer Design, pp.45-49, 2002 https://doi.org/10.1109/ICCD.2002.1106746
- R.-M. Kling and P. Banerjee, 'ESP: A New Standard Cell Placement Package Using Simulated Evolution,' Proc. of DAC, pp. 60-66, 1987 https://doi.org/10.1145/37888.37897
- T. Chan, J. Cong, T. Kong, and J. Shinnerl, 'Multilevel Optimization for Large-Scale Circuit Placement.' Proc. of ICCAD, pp.171-176, 1999 https://doi.org/10.1109/ICCAD.2000.896469
- 허성우, 오은경, '표준 셀 배치를 위한 하이브리드 기법,' 정보과학회 논문지: 시스템 이론, Vol.30, No.9.10, pp.595-602, 2003
- G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, 'Multilevel Hypergraph Partitioning: Application in VLSI Domain,' Proc. of DAC, pp.526-529, 1997 https://doi.org/10.1145/266021.266273
- C. J. Alpert and A. B. Kahng, 'A General Framework for Vertex Orderings, with Applications to Netlist Clustering,' Proc. of ICCAD, pp.63-67, 1994
- S. N. Adya, M. C. Yildiz, I. L. Markov, P. G. Villarrubia, P. N. Parakh, and P. H. Madden, 'Benchmarking for Large-Scale Placement and Beyond,' Proc. of ISPD, pp. 95-103, 2003 https://doi.org/10.1145/640000.640022
- http://vlsicad.eecs.umich.edu/BK