The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
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Automatic Verification of the Control Flow Model for Effective Embedded Software Design

효과적인 임베디드 소프트웨어 설계를 위한 제어흐름 모델의 자동 검증

  • 박사천 (경기대학교 전자계산학과) ;
  • 권기현 (경기대학교 정보과학부) ;
  • 하순회 (서울대학교 컴퓨터공학과)
  • Published : 2005.12.01
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Abstract

Hardware and software codesign framework called PeaCE(Ptolemy extension as a Cod sign Environment) allows to express both data flow and control flow. To formally verify an fFSM specification which expresses control flow in PeaCE, the step semantics of the model was defined. In this paper, we introduce the automatic verification tool developed by formal semantics of previous work. This tool uses the SMV as inner model checker md, through our tool, users can formally verify some important bugs such as race condition, ambiguous transition, and circulartransition without directly writing logical formulae.

하드웨어와 소프트웨어를 통합 설계하는 프레임워크인 PeaCE(Ptolemy extension as a Codesign Environment)에서는 데이터 흐름과 제어흐름을 모두 표현할 수 있다. PeaCE에서 제어 흐름을 표현하는 fFSM 명세를 정형 검증하기 위해 fFSM의 단계 의미를 정의하였다. 본 논문에서는 이전 연구에서 정의된 정형 의미를 바탕으로 개발한 자동 검증 도구를 소개한다. 이 도구는 내부 모델체커로 SMV를 사용하며 사용자는 직접 논리식을 기술하지 않고도 레이스 조건, 애매한 전이, 순환 전이 등의 주요한 버그들을 검증할 수 있다.

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References

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