대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

고속 저전력 VLSI를 위한 가변 샘플링 윈도우 플립-플롭의 설계

Variable Sampling Window Flip-Flops for High-Speed Low-Power VLSI

  • 신상대 (한국항공대학교 항공전자공학과) ;
  • 공배선 (성균관 대학교 정보통신공학부)
  • Shin Sang-Dae (Department of Avionics Engineering, Hankuk Aviation University) ;
  • Kong Bai-Sun (School of Information and Communication Engineering, Sungkyunkwan University)
  • 발행 : 2005.08.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 전력소모 감소 및 강건성 (robustness) 향상을 위한 새로운 구조의 플립-플롭을 제안한다. 가변 샘플링 윈도우 플립-플롭(Variable sampling window flip-flop, VSWFF)은 입력 데이터에 따라 샘플링 윈도우의 폭을 변화시켜 강인한 데이터-래치 동작을 제공할 뿐 아니라 더욱 짧은 hold time을 갖는다. 또한, 이 플립-플롭은 입력 스위칭 행위(input switching activity)가 큰 경우에 기존의 저전력 플립-플롭보다 내부 전력소모를 감소시킬 수 있다. 클럭 진폭 감쇄형 가변 샘플링 윈도우 플립-플롭(Clock swing-reduced variable sampling window flip-flop, CSR-VSWFF)은 작은 스윙 폭의 클럭을 사용함으로써 클럭분배망(clock distribution network)의 전력소모를 감소시킬 수 있다. 기존의 클럭 진폭 감쇄형 플립-플롭(Reduced clock swing flip-flop, RCSFF)과 달리, 제안된 플립-플롭은 공급전압만으로 동작하므로 고전압의 발생 및 분배로 인한 설계 상의 비용증가를 제거한다. 시뮬레이션 결과, 기존의 플립-플롭과 비교하여 더욱 좁은 샘플링 윈도우에서도 불변의 지연값(latency) 을 유지하고 전력-지연 곱(power-delay product, PDP)이 개선됨을 확인하였다. 제안된 플립-플롭의 성능을 평가하기 위하여 $0.3\mu m$ CMOS 공정기술을 이용하여 테스트 칩을 설계하였으며, 실험 결과, VSWFF는 입력 스위칭 행위가 최대일 때 전력소모가 감소하며 CSR-YSWFF를 이용하여 설계된 동기 카운터는 부가 고전압의 사용 없이 전력소모가 감소됨을 확인하였다.

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

키워드

참고문헌

  1. N. Weste, and K. Eshragian, Principles of CMOS VLSI design: A systems perspective. Reading. MA: Addison-Wesley, pp. 145-149, 1986
  2. J. M. Labaey, et al., Low power design methodologies, Norwell, MA: Kluwer Academic, 1996
  3. V. Stojanovic, et al., 'Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,' IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536-548, April 1999 https://doi.org/10.1109/4.753687
  4. B. Nikolic, et al., 'Improved sense amplifier-based flip-flop: design and measurements,' IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-884, June 2000 https://doi.org/10.1109/4.845191
  5. B.-S. Kong, et al., 'Conditional-capture flip-flop for statistical power reduction,' IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263-1271, August 2001 https://doi.org/10.1109/4.938376
  6. H. Kawaguchi, et al., 'A reduced clock-swing flip-flop (RCSFF) for 63% power reduction,' IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807-811, May 1998 https://doi.org/10.1109/4.668997
  7. S. M. Mishra, et al., 'A high performance double edge-triggered flip-flop using a merged feedback technique,' IEE Proceedings-Circuits, Devices and Systems, vol. 147, no. 6, pp. 363-368, Dec. 2000 https://doi.org/10.1049/ip-cds:20000687
  8. S. M. Mishra, et al., 'A methodology to design high performance double edge-triggered flip-flops,' IEE Proceedings-Circuits, Devices and Systems, vol. 147, no. 5, pp. 283-290, Oct. 2000 https://doi.org/10.1049/ip-cds:20000672
  9. M. Hashimoto and D.-K. Jeong, 'Small to full swing conversion circuit', U.S. Patent 5,332,934, July 1994
  10. S.-D. Shin, et al., 'Variable sampling window flip-flop for low-power application,' IEEE Int. Symp. on Circuits and Systems, Dig. of Tech. Papers, pp. 257-260, May 2003 https://doi.org/10.1109/ISCAS.2003.1206247