A New Low Power LFSR Architecture using a Transition Monitoring Window

천이 감시 윈도우를 이용한 새로운 저전력 LFSR 구조

  • Kim Youbean (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Yang Myung-Hoon (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Lee Yong (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Park Hyuntae (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang Sungho (Department of Electrical and Electronic Engineering, Yonsei University)
  • 김유빈 (연세대학교 전기전자공학과) ;
  • 양명훈 (연세대학교 전기전자공학과) ;
  • 이용 (연세대학교 전기전자공학과) ;
  • ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2005.08.01

Abstract

This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random gaussian distribution. The Proposed technique represses transitions of patterns using a k-value which is a standard that is obtained from the distribution of U to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the Proposed BIST TPG schemes can reduce scan transition by about $60\%$ without performance loss in ISCAS'89 benchmark circuits that have large number scan inputs.

본 논문은 새로운 저전력 BIST 패턴 생성기에 대해 제안하고 있다. 이는 천이 감시 윈도우 블록과 MUX로 구성된 천이 감시 윈도우를 사용하는데, LFSR(linear feedback shift register)에서 생성되는 무작위 테스트 패턴의 패턴 천이 수 분포가 유사 무작위 가우시안(pseudo-random gaussian) 분포를 보이는 성질을 이용한다. 제안된 방식에서 천이 감시 윈도우는 스캔 체인에서 높은 전력 소모의 원인이 되는 초과 천이를 감지하고, k-value라는 억제 천이 수를 통해 초과 천이를 억제하는 역할을 한다 ISCAS'89 벤치마크 회로 중 많은 수의 스캔 입력을 갖는 회로를 사용하여 실험한 결과, 성능 손실 없이 약 $60\%$정도의 스캔 천이 수 감소를 나타내었다.

Keywords

References

  1. Nan-Cheng Lai and Sying- Jyan Wang, 'A Reseeding Technique for LFSR-Based BIST Applications', Proc, IEEE Asian Test Symposium (ATS) , 2002, pp. 200-205 https://doi.org/10.1109/ATS.2002.1181711
  2. Seongmoon Wang, 'Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST', Proc. IEEE International Test Conference (ITC), 2002, pp. 834-843 https://doi.org/10.1109/TEST.2002.1041837
  3. Xiaodong Zhang and Kaushik Roy, 'Peak Power Reduction in Low Power BlST', Proc. ISQED, 2000, pp. 425-432
  4. S. Wang, and K. Gupta, 'DS-LFSR : A New BIST TPG for Low Heat Dissipation', Proc. IEEE International Test Conference (ITC), 1997, pp. 848-857 https://doi.org/10.1109/TEST.1997.639699
  5. X. Zhang, K. Roy, and S. Bhawmik, 'POWERTEST : A Tool for Energy Conscious Weighted Random Pattern Testing', Proc. The 12th International Conference on VLSI Design, 1999, pp. 416-422 https://doi.org/10.1109/ICVD.1999.745191
  6. S. Wang, and K. Gupta, 'LT-RTPG : A New Test-Per-Scan BIST TPG for low Heat Dissipation', Proc. IEEE International Test Conference (ITC), 1999, pp. 85-94 https://doi.org/10.1109/TEST.1999.805617
  7. N. Ahmed, M. H. Teharanipour, and M. Nourani, 'Low Power Pattern Generation for BIST Architecture', proc. IEEE ISCAS, 2004, pp. 689-692
  8. Nadir Z. Basturkmen, Sudhakar M. Reddy, and Irith Pomeranz, 'A Low Power Pseudo-Random BIST Technique', proc. IOLTS, 2002, pp. 140-144 https://doi.org/10.1109/OLT.2002.1030197
  9. S. Wang, 'Low Hardware Overhead Scan Based 3-Weighted Weighted Random BIST', Proc. IEEE International Test Conference (ITC), 2001, pp. 868-877
  10. S. Manich, A. Gabarro, M. Lopez, and J. Figueras, 'Low Power BIST by Filtering Non-Detecting Vectors', Proc. IEEE Test workshop, 1999, pp. 165-170 https://doi.org/10.1109/ETW.1999.804524
  11. He Ronghui, Li Xiaowei, and Gong Yunzhan, 'A Low Power BIST TPG Design', Proc. IEEE 5th International ASIC Conference, 2003, pp. 1136-1139
  12. Kenneth M. Butler, Jayashree Saxena, Tony Fryars, and Graham Hethrington, 'Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques', Proc. IEEE International Test Conference (ITC), 2004, pp. 355-364 https://doi.org/10.1109/TEST.2004.1386971
  13. Debjyoti Ghosh, Swarup Bhunia, and Kaushik Roy, 'A Technique to Reduce Power and Test Application Time in BIST', Proc. IEEE International On-Line Testing Symposium (IOLTS), 2004, pp. 182-183
  14. C. Y. Tsui, J. Rajski, and M. Marek0Sadowska, 'Star Test: The Theory and Its Applications', IEEE Trans. On Computer-Aided Design of Integrated Circuit and System, Vol. 19(9), September 2000, pp. 1052-1064 https://doi.org/10.1109/43.863645
  15. Y. Zorian, 'A Distributed BIST Control Scheme for Complex VLSI Devices', Proc. VLSI Testing Symposium, 1993, pp. 4-9 https://doi.org/10.1109/VTEST.1993.313316