대한전자공학회논문지SP (Journal of the Institute of Electronics Engineers of Korea SP)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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협대역 응용 시스템을 위한 전처리기-등화기 구조의 IIR 여파기 설계 방법

Design of IIR Filters with Prefilter-Equalizer Structure for Narrowband Applications

  • 발행 : 2005.07.01
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초록

본 연구는 협대역 응용 시스템을 위한 전처리기-등화기 구조의 여파기에서, 최소의 복잡도를 갖는 곱셈기 없는 디지털 IIR 여파기의 설계 방식을 제안한다. 제안하는 여파기는 순환 다항식 (cyclotomic polynomial (CP)) 여파기와 1차 내삽 다항식(interpolated second order polynomial (EOP))을 근간으로 하는 al1-pole 등화기로 구성 되며, 이 두 여파기가 동시에 혼합 정수 선형계획법(miked integer linear programming (MILP))으로 최적 설계된다. 설계된 여파기는 최소의 복잡도를 갖는 특성을 가지고 있다. 뿐만 아니라, 이 MILP 방식은 계산 복잡도와 위상 응답의 비선형 특성을 모두 최소화하도록 설계한다. 설계 예제를 통하여 제안된 설계 방식으로 설계된 여파기는 구현 요구사항을 만족하면서 기존의 설계 방식에 비하여 복잡도면에서 월등히 우수한 특성을 보임을 확인하였다.

Optimal methods for designing multiplierless IIR filters with cascaded prefilter-equalizer structures are proposed for narrowband applications. Assuming that an U filter consists of a cyclotomic Polynomial (CP) prefilter and an all-Pole equalizer based on interpolated first order polynomial (IFOP), in the proposed method the prefilter and equalizer are simultaneously designed using mixed integer linear programming (MILP). The resulting filter is a cascaded filter with minimal complexity. In addition, MtP tries to minimize both computational complexity and phase response non-linearity. Design examples demonstrate that the proposed methods produce a more efficient cascaded prefilter-equalizer than existing methods.

키워드

참고문헌

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