IE interfaces (산업공학)

Korean Institute of Industrial Engineers (대한산업공학회)
권호 표지

Methods and Sample Size Effect Evaluation for Wafer Level Statistical Bin Limits Determination with Poisson Distributions

포아송 분포를 가정한 Wafer 수준 Statistical Bin Limits 결정방법과 표본크기 효과에 대한 평가

  • Received : 20030900
  • Accepted : 20031200
  • Published : 2004.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

In a modern semiconductor device manufacturing industry, statistical bin limits on wafer level test bin data are used for minimizing value added to defective product as well as protecting end customers from potential quality and reliability excursion. Most wafer level test bin data show skewed distributions. By Monte Carlo simulation, this paper evaluates methods and sample size effect regarding determination of statistical bin limits. In the simulation, it is assumed that wafer level test bin data follow the Poisson distribution. Hence, typical shapes of the data distribution can be specified in terms of the distribution's parameter. This study examines three different methods; 1) percentile based methodology; 2) data transformation; and 3) Poisson model fitting. The mean square error is adopted as a performance measure for each simulation scenario. Then, a case study is presented. Results show that the percentile and transformation based methods give more stable statistical bin limits associated with the real dataset. However, with highly skewed distributions, the transformation based method should be used with caution in determining statistical bin limits. When the data are well fitted to a certain probability distribution, the model fitting approach can be used in the determination. As for the sample size effect, the mean square error seems to reduce exponentially according to the sample size.

Keywords

References

  1. Cheong, K., Kim,J., Son, H., Kim, K., Park, Y. and Yun,J. (1996), Studies on Construction of SBL System and Improvement for Process of Testing Semiconductor, Korean Semiconductor Technical Journal, 34, 1405-1418
  2. Cunningham, J. A. (1990), The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing, IEEE Transactions on Semiconductor Manufacturing, 3(2),60-71
  3. Illyes, S. and Baglee, D. A. G. (1992), Statistical Bin Limits-an Approach to Wafer Disposition in Ie Fabrication, IEEE Transactions on Semiconductor Manufacturing, 5(1), 59-61
  4. Law, A. M. and Kelton, W. D. (1991), Simulation Modeling and Analysis, 2nd edn, McGraw-Hill, New York
  5. Montgomery, D. C.(1997), Design and Analysis of Experiments, 4th edn, Wiley, New York
  6. Montgomery, D. C. (2001), Introduction to Statistical Quality Control, 4th edn, Wiley, New York
  7. Montgomery, D. C. and Peck, E. A. (1992), Introduction to Linear Regression Analysis, 2nd edn, Wiley, New York
  8. Myers, R. H. and Montgomery, D. C. (1995), Response Surface Methodology Process and Product Optimization Using Designed Experiments, Wiley, New York
  9. Park,K, Lee, J., Kim,K, Kim,B., Lee, Y. and Ban,K (2000), Development of SBL System for Effectively Detecting Process Variation and Continuous Process Improvement, Technical Report, No. GN-00101442, Device Solution Network, Samsung Electronics Co.,Ltd.