JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 9-bit ADC with a Wide-Range Sample-and-Hold Amplifier

  • Lim, Jin-Up (Department of Electrical and Computer Engineering, University of Seoul) ;
  • Cho, Young-Joo (Department of Electrical and Computer Engineering, University of Seoul) ;
  • Choi, Joong-Ho (Department of Electrical and Computer Engineering, University of Seoul)
  • Published : 2004.12.31
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Abstract

In this paper, a 9-bit analog-to-digital converter (ADC) is designed for optical disk drive (ODD) servo applications. In the ADC, the circuit technique to increase the operating range of the sample-and-hold amplifier is proposed, which can process the wide-varying input common-mode range. The algorithmic ADC structure is chosen so that the area can be significantly reduced, which is suitable for SoC integration. The ADC is fabricated in a 0.18-$\mu\textrm{m} $ CMOS 1P5M technology. Measurement results of the ADC show that SNDR is 51.5dB for the sampling rate of 6.5MS/s. The power dissipation is 36.3mW for a single supply voltage of 3.3V.

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References

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