References
- IEEE P1500 Standard for Embedded Core Test (http://grouper.ieee.org/groups/P1500)
- J. Aerts and E. J. Marinissen, 'Scan chain design for test time reduction in core-based ICs', Proceedings of International Test Conference, pp. 448-457, 1998 https://doi.org/10.1109/TEST.1998.743185
- M. L. Bushnell and V. D. Agrawal, 'Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits', Kluwer Academic Publ., ISBN 0-7923-7991-8
- E. J. Marinissen, S. K. Goel and M. Lousberg, 'Wrapper design for embeded core test', Proceedings of International Test Conference, pp. 911-920, 2000 https://doi.org/10.1109/TEST.2000.894302
- R. L. Graham, 'Bounds on multiprocessing anomalies', SIAM Journal of Applied Mathematics, Volume 17, pp. 416-429, 1969 https://doi.org/10.1137/0117039
- E. Larsson and Hideo Fujiwara, 'Power constrained preemptive TAM scheduling', Proceedings of the Seventh IEEE European test Workshop, 2002 https://doi.org/10.1109/ETW.2002.1029648
- Wei Zou, S. M. Reddy, I. Pomeranz and Yu Huang, 'SOC test scheduling using simulated annealing', VLSI Test Symposium, 2003. Proceedings. 21st, pp. 325-330, 27 April - 1 May 2003 https://doi.org/10.1109/VTEST.2003.1197670
- P. Varma and B. Sandeep, 'A structured test re-use methodology for systems on silicon', Proceedings of International Test Conference, pp. 294-302, 1998 https://doi.org/10.1109/TEST.1998.743167
- ITC'02 (International Test Conference) SOC Benchmarks (http://www.extra.research.philips.com/itc02socbench.com/)
- E. G. Coffman Jr., M. R. Garey and D. S. Johnson, 'An application of bin-packing to multiprocessor scheduling', SIAM Journal of Computing, Volumn 7, Number 1, pp. 1-17, 1978 https://doi.org/10.1137/0207001
- C. Sunghoon, Y. Kim, Y. Shin, S. Song and S. Kang, 'A new functional delay fault ATPG for embedded cores', Proceedings of the 4th Korea Test Conference, pp. 159-164, 2003
- V. Iyengar, K. Chakrabarty and E. J. Marinissen, 'Test wrapper and test access mechanism co-optimization for system-on-chip', Proceedings of International Test Conference (ITC02), pp. 1023-1032, 2001 https://doi.org/10.1109/TEST.2001.966728
- S. Koranne, 'On test planning for core-based SOCs', Proceedings of ECCO XIV, 2001
- S. Koranne, 'Design of reconfigurable access wrappers for embedded core based SOC test', Proceedings of the International Symposium on Quality Electronic Design (ISQED02), pp. 106-111, 2002 https://doi.org/10.1109/ISQED.2002.996707
- V. Iyengar, K. Chakrabarty and E. J. Marinissen, 'On using rectangle packing for SOC wrapper/TAM co-optimization', Proceedings of VLSI Test Symposium, 2002. (VTS 2002), pp. 253-258, 2002 https://doi.org/10.1109/VTS.2002.1011146
- S. Koranne, 'Formulating SOC test scheduling as a network transportation problem', Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume: 21 Issue: 12, pp. 1517-1525, 2002 https://doi.org/10.1109/TCAD.2002.804382
- S. Koranne and V. Iyengar, 'On the use of k-tuples for SOC test schedule representation', Proceedings of International Test Conference (ITC02), pp. 539-548, 2002 https://doi.org/10.1109/TEST.2002.1041804