정보처리학회논문지C (The KIPS Transactions:PartC)

한국정보처리학회 (Korea Information Processing Society)
권호 표지
DOI QR코드

DOI QR Code

네트워크 프로세서를 위한 다중 쓰레드 스케줄링

Multi-thread Scheduling for the Network Processor

  • 임강빈 (순천향대학교 정보보호학과) ;
  • 박준구 (디지털스트림테크놀로) ;
  • 정기현 (아주대학교 전자공학) ;
  • 최경희 (아주대학교 정보 및 컴퓨터공학부)
  • 발행 : 2004.06.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 다중 프로세서(Multiprocessor) 기반 다중 쓰레드(Multithreaded) 구조의 네트워크 프로세서를 이용한 패킷 치리 시스템에서 패킷을 보다 고속으로 처리하기 위한 쓰레드 스케줄링 기법을 제안한다 이를 위하여 스케줄링과 관련한 인자를 실험을 통하여 얻고, 패킷 내용 및 다중 쓰레드 아키텍쳐를 표현하는 인자를 포함하도록 설계하였다. 시뮬레이터를 이용한 실험을 통하여 제안된 스케줄링 기법이 제공하는 처리율 및 부하 분산 정도가 다른 스케줄링 기법과 비교하여 효율적임을 증명하였다.

In this paper, we propose a thread scheduling algorithm for faster packet processing on the network processors with multithreaded multiprocessor architecture. To implement the proposed algorithm. we derived several basic parameters related to the thread scheduling and included a new parameter representing the packet contents and the multithreaded architecture. Through the empirical study using a simulator, we proved the proposed scheduling algorithm provides better throughput and load balancing compared to the general thread scheduling algorithm.

키워드

참고문헌

  1. A. Campbell, H. De Meet, M. Kounavis, K. Miki, J. Vicente, and D. Villela, 'A Survey of Programmable Networks,' ACM Computer Communications Review, April, 1999 https://doi.org/10.1145/505733.505735
  2. P. Crowley, M. E. Fiuczynski, J.-L. Baer and B. N. Bershad, 'Characterizing processor architectures for programmable network interfaces,' Proceedings of the International Conference on Supercomputing, 2000 https://doi.org/10.1145/335231.335237
  3. Niraj Shah, Kurt Keutzer, 'Network Processors : Origin of Species,' Proceedings of ISCIS XVII, The Seventeenth International Symposium on Computer and Information Sciences, October, 2002
  4. T. Wolf and M. A. Franklin, 'Locality-aware predictive scheduling for network processors,' Proc. of IEEE international Symposium of Performance Analysis of Systems and Software(ISPASS), Tucson, AZ, Nov., 2001
  5. D. J. Lilja, 'Exploiting the Parallelism Available in Loops,' IEEE Computer, Vol.27, No.2, pp.13-26, 1994 https://doi.org/10.1109/2.261915
  6. S. Baruah, J. Gehrke and C. G. Plaxton, 'Fast scheduling of periodic tasks on mutiple resources,' Proc. of the 9th International Parallel Processing Symposium, pp.280-288, Apr., 1995 https://doi.org/10.1109/IPPS.1995.395946
  7. K. P. Hung, N. H. C. Yung, and Y. S. Cheung, 'Multithreaded self-scheduling : Application of multithreading on loop scheduling for distributed shared memory multiprocessor,' IEEE International Conference on Algorithms and Architectures for Parallel Processing, Brisbane, Australia, April, 1995 https://doi.org/10.1109/ICAPP.1995.472255
  8. C. Polychronopoulos and D. Kuck, 'Guided Self-Scheduling : Practical Scheduling Scheme for Parallel Supercomputers,' IEEE Transactions on Computers, Vol.C-36, No.12, pp.1425-1439, December, 1987 https://doi.org/10.1109/TC.1987.5009495
  9. Ten H. Tzen and Lionel M. Ni, 'Trapezoid Self-Scheduling: Practical Scheduling Scheme for Parallel Supercomputers,' IEEE Transactions on Parallel and Distributed Systems, Vol.4, No.1, pp.87-98, January, 1993 https://doi.org/10.1109/71.205655
  10. Nie, X., Gazsi, L., Engel, F., Fettweis, G., 'A New Network Processor Architecture for High-Speed Communications,' Proc. of IEEE Workshop on Signal Processing Systems, Taipei/Taiwan, Oct., 1999 https://doi.org/10.1109/SIPS.1999.822361
  11. V. Srinivasan and G. Varghese and S. Suri and M. Waldvogel, 'Fast and Scalable Layer four Switching,' Proceedings of ACM SIGCOMM, pp.191-202, 1998 https://doi.org/10.1145/285237.285282
  12. National Laboratory for Applied Network Research, http://www.nlanr.net
  13. Intel IXP1200 Network Processor Family, Hardware Reference Manual, Intel Corp. December, 2001
  14. Intel IXP1200 Network Processor Family, Development Tools user's Guide, Intel, December, 2001