나노기술 환경에 적합한 차세대 정보 보호 프로세서 구조와 연산 회로 기술 연구

  • 최병윤 (동의대학교 컴퓨터공학과) ;
  • 이종형 (동의대학교 전자공학과) ;
  • 조현숙 (한국전자통신연구원 정보보호기반연구팀)
  • Published : 2004.04.01

Abstract

정보 통신과 반도체 공정 기술의 급격한 발전으로 나노기술이 가까운 시일 내에 실용화되고, 유비쿼터스 환경이 도래할 것으로 예측된다. 나노기술 환경에서 사용되는 디바이스의 고집적도, 낮은 구동 능력, 배선 제약 특성이 정보 보호 분야에 사용되는 프로세서 구조와 회로 설계 기술을 크게 바꿀 것으로 예측된다. 본 연구에서는 이러한 기술 변혁에 대비하기 위해 나노기술 환경에 적합한 차세대 정보 보호 프로세서 구조와 회로 설계 기술을 분석하였다.

Keywords

References

  1. '98 International Conference of Semiconductors v.2 From Micro- To Nano- Technologies Dan DASCALU
  2. Technology Roadmap for Nano electronics (2nd ed.) ITRS
  3. Technology Roadmap for Nano-electronics ITRS
  4. International Technology Roadmap for Semiconductors ITRS
  5. Ultra electronics program review Novel processor arrays for nanoelectronics Fountain,T.J.;D.G.Crawley;M.R.B.Forshaw;S.Spagocci;D.Berzon
  6. IEEE Trans. On Very Large Scale Integrated Systems v.6 The use of nano-electronic devices in highly parallel computing systems Fountain,T.J.;M.J.B.Duff;D.G.Crawley;C.D.Tomlinson;C.D.Moffat https://doi.org/10.1109/92.661242
  7. Technologies and Designs for Electronic Nanocomputers Montemelo,M.;Love,C.;Opiteck,G.;Goldhaber Gordon;D.Ellenbogen
  8. 7th Asia-Pacific Computer Systems Architecture Conference in Research and Practice in Information Technology (ACSAC '2002) Towards Nanocomputer Architecture Paul Becket;Addrew Jennings
  9. 24th European Solid-State Circuits Conference (ESSCIRC'98) System and Circuit Aspect of Nanoelectronics Karl,F.Goser;Chrisina Pacha
  10. Proceedings of the IEEE v.85 no.4 Aspect of Systems and Circuits for Nanoelectronics Karl,F.Gosner;Christina Pacha https://doi.org/10.1109/5.573741
  11. Position Statement for the STORK (Strategic Roadmap for Cryptography) Workshop The future of the Art of Cryptographic Implementations Christof Paar
  12. Proceedings of the Workshop on Crytographic Hardware and Embedded System 1999(CHES '99) A High Performance Flexible Architecture for Cryptography R.Reed Taylor;Seth Copen Goldstein
  13. Science v.230 What makes a good computer device ? R.W.Keyes https://doi.org/10.1126/science.230.4722.138
  14. Proc. IEEE v.89 CMOS scaling for highper-formance and low-power-the next ten years B.Davari;R.H.;Dennard;G.G.Shahidi
  15. Proc. IEEE v.89 Device Scaling Limits of si MOSFETs and Their Application Dependencies D.J.Frank(et al.) https://doi.org/10.1109/5.915374
  16. IEEE ASSP magazine VLSI array processor S.Y.Kung
  17. Ph. D dissertation Stanford University Globally-aynchronous, locally-synchronous systems D.M.Chapiro
  18. cryptography How secure are FPGAs in Cryptographic Applications? (Long Version) Thomas Wollinger;Christof Parr
  19. Proceedings of the IEEE v.86 no.9 Defect tolerance in VLSI circuits Israel Korean;zahava koren https://doi.org/10.1109/5.705525
  20. SPIE's symposium n voice, and data communications An Algorithm-Agile Cryptographic Co-Processor based on FPGAs Christof Paar;Brendon Chetwynd;Thomas Connor
  21. Multi-valued logic in VLSI : challenge and opportunities Elena Dubrova
  22. Non-silicon non-binary computing: Why not? Elena Dubrova;Yusuf Jamal;Jimson Mathew
  23. ETH Integrated System Laboratory, Ph. D thesis Binary adder architectures for cell-Based VLSI and their synthesis Reto Zimmermann