Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Dynamic Power Estimation Method of VLSI Interconnects

VLSI 회로 연결선의 동적 전력 소모 계산법

  • Published : 2004.02.01
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Abstract

Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals increase, power consumption associated with interconnects is ever-increasing. In case of clock trees, particularly power consumption associated with interconnects is over 30％ of total power consumption. Hence, an efficient method to compute power consumption of interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power consumption of interconnects. We propose a new reduced-order model to estimate power consumption of large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power consumption of whole interconnects can be approximated, and propose an analytical method to compute the power consumption. The results applying the proposed method to various RC networks show that average relative error is 1.86％ and maximum relative error is 9.82％ in comparison with HSPICE results.

현재까지 연결선을 타이밍(timing) 관점에서 해석하려는 시도들은 많았지만, 전력 소모의 관점에서 해석하려는 시도는 많지 않았다. 그러나 지금은 연결선의 저항 성분과 신호의 상승 시간이 점차 증가하는 추세에 따라 회로 연결선에서의 전력 소모가 증가하고 있는 시점이다. 특히, 클럭 신호선의 경우 칩 전체 전력 소모 중 30％ 이상을 차지하고 있다. 따라서 회로 연결선에서의 전력 소모를 효과적으로 계산하는 방법이 필요하며, 본 논문에서는 회로 연결선의 동적 전력 소모를 계산하는 간단하면서도 정확한 방법을 제시하고자 한다. 사이즈가 큰 연결선의 동적 전력 소모를 계산하기 위한 축소 모형을 제안하고, 이 축소모형을 구성하는 방법을 제시한다. 제안한 축소 모형의 해석을 통해 연결선 전체의 동적 전력 소모를 근사할 수 있음을 보이고, 이를 간단히 계산하는 방법을 제안 하고자 한다. 노드 수 100∼1000개까지 RC 회로에 대해 제안한 방법을 적용한 결과 연결선의 전력 소모는 HSPICE에 비해 1.86％의 평균 상대 오차 및 9.82％의 최대 상대 오차를 보였다.

Keywords

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