ETRI Journal

  • 제26권6호
  • /
  • Pages.545-554
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  • 2004
  • /
  • 1225-6463(pISSN)
  • /
  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
권호 표지

An Area Optimization Method for Digital Filter Design

  • Yoon, Sang-Hun (Department of Electronic Engineering, Hanyang University) ;
  • Chong, Jong-Wha (Department of Electronic Engineering, Hanyang University) ;
  • Lin, Chi-Ho (Department of Computer Science, Semyung University)
  • 투고 : 2004.02.25
  • 발행 : 2004.12.31
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초록

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

키워드

참고문헌

  1. Proc. IEEE Int’l. Symp. Circuits Systems Optimization of Canonical Signed Digit Multipliers for Filter Design Hartley, R.
  2. IEEE Trans. Computer-Aided Design v.15 no.2 Multiple Constant Multiplication: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination Potkonjak, M.(et al.)
  3. IEEE Trans. Circuits Syst. II v.42 Use of Minimum-Adder Multiplier Blocks in FIR Digital Filters Dempster, A.;Macleod, M.D.
  4. Proc. Inst. Ele. Eng. Circuits, Devices and Systems v.138 Primitive Operator Digital Filter Bull, D.R.;Horrocks, D.H.
  5. IEEE Trans. Circuits Syst. II v.43 Subexpression Sharing in Filters Using Canonical Signed Digit Multipliers Hartley, R.
  6. IEEE Trans. Circuits Syst. II v.49 no.3 Design of High-Speed Multiplierless Filters Using a Nonrecursive Signed Common Subexpression Algorithm Martinez-Peiro, M.;Boemo, E.I.;Wanhammar, L.
  7. Proc. IEEE Int’l Symp. Circuits and Systems FIR Digital Filter Implementation Using Flattened Coefficient Yoon, S.H.;Chong, J.W.
  8. IEEE Trans. Circuits Syst. II v.48 no.8 FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders Kang, H.J.;Park, I.C.
  9. Proc. IEEE Int’l Symp. Circuits and Systems Designing Multiplier Blocks with Low Logic Depth Dempster, A.;Demirsoy, S.;Kale, I.