The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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The Design of GF(2m) Parallel Multiplier using data select methodology

데이터 선택방식에 의한 GF(2m)상의 병렬 승산기 설계

  • 변기영 (인하대학교 전자공학과 회로및시스템 연구실) ;
  • 최영희 (인하대학교 전자공학과 회로및시스템 연구실) ;
  • 김흥수 (인하대학교 전자공학과 회로및시스템 연구실)
  • Published : 2003.02.01
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Abstract

In this paper, the new multiplicative algorithm using standard basis over GF(2m) is proposed. The multiplicative process is simplified by data select method in proposed algorithm. After multiplicative operation, the terms of degree greater than m can be expressed as a polynomial of standard basis with degree less than m by irreducible polynomial. For circuit implementation of proposed algorithm, we design the circuit using multiplexer and show the example over GF(24). The proposed architectures are regular and simple extension for m. Also, the comparison result show that the proposed architecture is more simple than privious multipliers. Therefore, it well suited for VLSI realization and application other operation circuits.

본 논문에서는 GF(2m)상의 표준기저를 사용한 새로운 형태의 승산 알고리즘을 제안하였다. 제안된 알고리즘에서 승산의 전개를 데이터 선택방식으로 취하여 연산과정을 단순화하였다. 승산연산의 결과 발생하는 m차 이상의 차수를 갖는 항에 대하여 기약다항식을 적용하여 m-1차 이하의 표준기저들로 나타나게 하였다. 제안된 알고리즘의 회로구현을 위해 멀티플렉서를 사용하여 회로를 구성하였고, GF(24)에 대한 설계의 예를 보였다. 새로운 승산회로는 그 구성이 규칙성을 가지며 m의 증가에 대한 확장이 용이하다. 또한, 타 논문과의 비교결과 사용소자의 수가 비교적 적다. 따라서, VLSI의 실현과 타 연산회로에의 적용에 적합하다 할 수 있다.

Keywords

References

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