Transactions on Electrical and Electronic Materials

  • 제4권6호
  • /
  • Pages.32-37
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  • 2003
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  • 1229-7607(pISSN)
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  • 2092-7592(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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Characteristics of Trap in the Thin Silicon Oxides with Nano Structure

  • Kang, C.S. (Department of Electronic Engineering, Yuhan College)
  • 발행 : 2003.12.01
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초록

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

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참고문헌

  1. S. Bruyere, E. Vincent, and G. Ghibaudo, 'Stress induced leakage current in very thin dielectric layers : some limitations to reliability extrapolation modeling', Microelectronics Reliability, Vol. 39, p. 209, 1999 https://doi.org/10.1016/S0026-2714(98)00207-8
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피인용 문헌

  1. Current Characteristics in the Silicon Oxides vol.29, pp.10, 2016, https://doi.org/10.4313/JKEM.2016.29.10.595