참고문헌
- J.P.Hayes, 'Testing Memories for Single-Cell Pattern-Sensitive Faults,' IEEE Trans. Comput., Vol. C-29, No. 3, March 1980 https://doi.org/10.1109/TC.1980.1675556
- J.P.Hayes, 'Detection of Pattern - Sensitive Faults in RAMs,' IEEE Trans. Comput., Vol. C-24, No. 2, pp. 150-157, Feb. 1975 https://doi.org/10.1109/T-C.1975.224182
- D.S.Suk and S.M.Reddy, 'Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories,' IEEE Trans. Comput., Vol. C-29, No. 6, pp. 419-429, June 1980 https://doi.org/10.1109/TC.1980.1675601
- P.Mazumder and J.K.Patel, 'Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories,' IEEE Trans. Comput., Vol. 38, No. 3, pp. 394-407, March 1989 https://doi.org/10.1109/12.21126
- A.J.van de Goor, 'Testing Semiconductor Memories,' John Wiley & Sons LTD., 1991
- A.K.Sharma, 'Semiconductor Memories,' IEEE PRESS, pp. 151-154, 1996
- S.Chou et al., 'A 60-ns 16Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance,' IEEE J. Solid State Circuits, Vol. 24, No. 5, pp. 1176-1183, October 1989 https://doi.org/10.1109/JSSC.1989.572575
- H.Hidaka et al., 'Twisted Bit-line Architectures for Multi-Megabit DRAM's,' IEEE J. Solid-State Circuits, Vol. 24, No. 1, pp. 21-27, February 1989 https://doi.org/10.1109/4.16297
- Y.Watanabe et al., 'Offset Compensating Bit-line Sensing Scheme for High Density DRAM's,' IEEE J. Solid-State Circuits, Vol. 29, No. 1, pp. 9-13, January 1994 https://doi.org/10.1109/4.272089
- D.S.Min and D.W. Langer, 'Multiple Twisted Dataline Techiques for Multigiga bit DRAM's,' IEEE J. Solid-State Circuits, Vol. 34, No. 6, pp. 856-864, June 1999 https://doi.org/10.1109/4.766820
- J.S.Kim et al., 'A Low-Noise Folded Bit-Line Sensing Architecture for Multigigabit DRAM with Ultrahigh-Density 6F2 cell,' IEEE J. Solid-State Circuits, Vol. 33, No. 7, pp. 1096-1102, July 1998 https://doi.org/10.1109/4.701271
- K.Kim and M.Y.Jeong, 'The COB Stack DRAM Cell at Technology Node Below 100nm-Scaling Issues and Directions,' IEEE Trans. Semi., Vol. 15, No. 2, pp. 137-143, May 2002 https://doi.org/10.1109/66.999584
- D.C.Kang and S.B.Cho, 'A New Test Algorithm for Bit-Line Sensitive Faults in High-Density Memories,' J. IKEEE, Vol. 5, No. 1, pp. 43-51, January 2001
- Dong-Chual Kang, Jong-Hwa Lee, and Sang-Bock Cho, 'A new test algorithm for bit-line sensitive faults in super high-density momories,' KORUS'01 Proceeding, The Fifth Russian-Korean International Symposium on Science and Technology, Volume 1, pp. 198-201, 2001 https://doi.org/10.1109/KORUS.2001.975099
- A.Kinoshita et al., 'A study of delay time on bit-lines in megabit SRAMs,' IEICE Trans. Electron Devices, Vol. E75-C, No. 11, November 1992, pp. 1383-1386