전자공학회논문지SC (Journal of the Institute of Electronics Engineers of Korea SC)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

완전탐색 블럭정합 알고리즘을 위한 일차원 시스톨릭 어레이의 구조

An Architecture of One-Dimensional Systolic Array for Full-Search Block Matching Algorithm

  • 이수진 (釜慶大學校, 電子컴퓨터情報通信工學部) ;
  • 우종호 (釜慶大學校, 電子컴퓨터情報通信工學部)
  • Lee, Su-Jin (Division of Electronics Computer and Communication Eng., Pukyong National University) ;
  • Woo, Chong-Ho (Division of Electronics Computer and Communication Eng., Pukyong National University)
  • 발행 : 2002.09.01
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초록

본 논문에서는 움직임 추정을 위한 블럭정합 알고리즘의 고속 처리를 위한 VLSI 어레이의 구조를 설계하였다. 완전탐색 블럭정합 알고리즘의 데이터 의존관계로부터 일차원 시스톨릭 어레이를 유도했다. 제안된 일차원 시스톨릭 어레이에 입력된 데이터와 제어신호는 인접한 처리요소를 통해서 전달되어 재사용된다. 따라서 제안된 시스톨릭 어레이는 시간 및 공간적 지역성을 만족한다. 데이터와 제어신호의 입출력 핀은 일차원 어레이의 시작과 끝의 처리요소에만 존재한다. 이 구조는 입력포트의 수가 적으며, 모듈러 확장성을 갖는다. 기준블럭과 최대탐색거리가 확장된 경우에 제안된 어레이를 연결하여 움직임 추정기를 구성할 수 있다.

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.

키워드

참고문헌

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