Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Design of a 2.5V 10-bit 300MSPS CMOS D/A Converter

2.5V 10-bit 300MSPS 고성능 CMOS D/A 변환기의 설계

  • 권대훈 (東國大學校 半導體科學科) ;
  • 송민규 (東國大學校 半導體科學科)
  • Published : 2002.07.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a 2.5V 10-bit 300MSPS CMOS D/A Converter is described. The architecture of the D/A Converter is based on a current steering 8+2 segmented type, which reduces non-linearity error and other secondary effects. In order to achieve a high performance D/A Converter, a novel current cell with a low spurious deglitchnig circuit and a novel inverse thermomeer decoder are proposed. To verify the performance, it is integrated with $0.25{\mu}m$ CMOS 1-poly 5-metal technology. The effective chip area is $1.56mm^2$ and power consumption is about 84mW at 2.5V power supply. The simulation and experimental results show that the glitch energy is 0.9pVsec at fs=100MHz, 15pVsec at fs=300MHz in worst case, respectively. Further, both of INL and DNL are within ${\pm}$1.5LSB, and the SFDR is about 45dB when sampling, frequency, is 300MHz and output frequency is 1MHz.

본 논문에서는 CMOS로 구현된 2.5v 10-bit 300MSPS의 D/A 변환기를 제안하였다. 이를 위해 전체구조는 고속동작에 유리한 전류구동 방식의 8+2 분할 타입으로 상위 8-bit은 Thermometer Code 기법을 이용한 전류셀 매트릭스(Current Cell Matrix)로, 하위 2-bit은 이진 가중 전류열(Binary Weighted Current Array)로 설계하였다. 우수한 다이내믹 특성 및 고속 동작을 만족시키기 위해 낮은 글리치 에너지를 갖는 새로운 전류셀과 BDD(Binary Decision Diagram)에 의한 논리합성 기법을 활용한 새로운 역 Thermometer Decoder를 제안하였다. 제안된 DAC는 $0.25{\mu}m$, 1-Poly, 5-Metal, n-well CMOS 공정으로 제작되었으며, 유효 칩 면적은 $1.56mm^2$이고, 2.5V의 전원전압에서 84mW의 전력소모를 나타내었다. 모의실험 및 측정을 통해 최대 글리치 에너지는 0.9pVsec@fs=100MHz, 15pVsec@fs=300MHz로 나타났다. 또한 출력 주파수가 1MHz, 샘플링 주파수가 300MHz에서의 INL과 DNL은 약 ${\pm}$1.5LSB 이내로, SFDR은 45dB로 측정되었다.

Keywords

References

  1. David A. Johns and Ken Martin, 'Analog Integrated Circuit Design', John Wiley & Sons Inc., 1997, pp. 445-486
  2. Mikael Gustavsson, J. Jacob Wikner, Nianxiong Nick Tan, 'CMOS Data Converters for Communications', Kluwer Academic Publishers., 2000, pp. 1-25, pp. 353-378
  3. Jose Bastos, 'A 12-Bit Intrinsic Accuracy High Speed CMOS DAC' IEEE J. Solid-State Circuits, Vol. 33, No. 12, pp. 1959-1969, Dec. 1998 https://doi.org/10.1109/4.735536
  4. Chi Hung Lin and Klaas Bult, 'A 10-b 500Msample/s CMOS DAC in 0.6mm' IEEE J. Solid-State Circuits, Vol. 33, No. 12, pp. 1948-1958, Dec. 1998 https://doi.org/10.1109/4.735535
  5. Cornelis A. A. Bastiaansen, D Wouter J. Groeneveld, Hans J.Schouwenaars and Henk A. H. Termeer, 'A 10b 40MHz 0.8um CMOS Current Output D/A Converter' IEEE J. Solid-State Circuits, Vol. 26, No. 7, pp. 917-921, July 1991 https://doi.org/10.1109/4.92010
  6. Shu Yuan Chin and Chung Yu Wu, 'A 10b 125MHz CMOS Digital-to-Analog (DAC) with Threshold Voltage Compensated Current Sources' IEEE J. Solid-State Circuits, Vol. 29, No. 11, pp. 1374-1380, November 1994 https://doi.org/10.1109/4.328639
  7. A. Fraval and F. Dell'ova 'A 10b 70MHz 3.3V CMOS 0.5um D/A Converter for Video Applications' IEEE Trans. Consumer Electronics, Vol. 41, No. 3, pp. 875-879, August 1995 https://doi.org/10.1109/30.468071
  8. Nianxiong Tan, Ellie Cijvat, Hannu Tenhunen, 'Design and Implementation of High Performance CMOS D/A Converter' IEEE ISCS, Hang Kong, June 9-12, 1997 https://doi.org/10.1109/ISCAS.1997.608757
  9. Nianxiong Tan, 'A 1.5V 3mW 10bit 50Ms/s CMOS DAC with Low Distortion and Low Intermodulation in Standard Digital CMOS Process' IEEE CICC'97, pp. 599-602, Santa Clara, CA, USA, May 1997 https://doi.org/10.1109/CICC.1997.606697
  10. Jin Park, Seung-Chul Lee, Seung-Hoon Lee, 'A 3V 10b 70MHz Digital to Analog Converter for Video Applications' AP-ASIC'99. The First IEEE Asia Pacific Conference on, 1999, pp. 186-189 https://doi.org/10.1109/APASIC.1999.824059
  11. A. Van den Bosch, M. Borremans, M. Steyaert, W Sansen, 'A 10-Bit 1 GSample/s Nyquist Current-Steering CMOS D/A Converter' IEEE Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000, pp. 265-268 https://doi.org/10.1109/CICC.2000.852663
  12. J. H. Kim and K. S. Yoon, 'An 8-Bit CMOS 3.3V 65MHz Digital to Analog Converter with a Symmetric Two-Stage Current Cell Matrix Architecture' IEEE Trans. Circuits Systs. II, Vol. 45, No. 12, pp. 1605-1609, Dec. 1998 https://doi.org/10.1109/82.746683
  13. 박진, 김창호, 이승훈, '고속 영상신호 처리를 위한 3V 12b 70MHz CMOS D/A 영상신호처리용 CMOS D/A변환기' IDEC MPW 발표회 논문집 pp. 191-196
  14. 이승훈, 전병렬, 윤상원, 이승훈 '높은 선형성을 가진 3V 10b 영상신호 처리용 CMOS D/A변환기' 전자공학회 논문지, Vol. 34C, No. 6, pp. 28-36, 1997
  15. 류기홍, '12비트 CMOS 전류셀 매트릭스 D/A 변환기 설계' 전자공학회 논문지, Vol. 36C, No. 8, pp. 10-21, 1999
  16. 이승훈, 김범섭, 송민규, 최중호 공저, 'CMOS 아날로그 / 혼성모드 집적 시스템 설계(상)', 시그마프레스, 1999, pp. 98-106
  17. 이승훈, 김범섭, 송민규, 최중호 공저, 'CMOS 아날로그 / 혼성모드 집적 시스템 설계(하)', 시그마프레스, 1999, pp. 91-98
  18. 박홍준, 'CMOS 아날로그 집적회로 설계(상)', 시그마프레스, 1999, pp. 451-459
  19. Abdellatif Bellaouar and Mohamed I. Elmasry, 'Low-Power Digital Design Circuits and Systems', Kluwer Academic Publishers, 1995, pp. 203-214