The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
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A Dynamic Routing Algorithm Adaptive to Traffic for Multistage Bus Networks in Distributed Shared Memory Environment

분산 공유메모리 환경의 다단계 버스망에서 트래픽에 적응하는 동적 라우팅 알고리즘

  • 홍강운 (한국전자통신연구원 네트워크연구소) ;
  • 전창호 (한양대학교 전자컴퓨터공학부)
  • Published : 2002.12.01
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Abstract

This paper proposes an efficient dynamic routing algorithm for Multistage Bus Networks(MBN's) in distributed shared memory environment. Our algorithm utilizes extra paths available on MBN and determines routing paths adaptively according to switch traffic in order to distribute traffic among switches. Precisely, a packet is transmitted to the next switch on an extra path having a lighter traffic. As a consequence the proposed algorithm reduces the mean response time and the average number of waiting tasks. The results of simulations, carried out with varying numbers of processors and varying switch sizes, show that the proposed algorithm improves the mean response time by 9% and the average number of waiting tasks by 21.6%, compared to the existing routing algorithms which do not consider extra paths on MBN.

본 논문은 분산 공유메모리 환경의 다단계 버스망을 위한 동적 라우팅 방범을 제안한다. 제안된 라우팅 방법의 특징은 다단계 버스망이 제공하는 잉여경로를 활용하고 스위치 트래픽에 따라 적응적으로 경로를 결정하여 스위치의 트래픽을 분산시키는 것이다. 구체적으로는 잉여경로 상의 다음 단계 스위치의 트래픽 정도가 높고 낮음을 판단하여 트래픽 정도가 낮은 스위치로 패킷을 전달한다. 그 결과 평균 응답시간과 스위치상의 평균 대기패킷수를 줄이는 효과를 얻는다. 프로세서수와 스위치 크기를 변화시키면서 시뮬레이션을 하여 제안된 알고리즘이 잉여경로를 고려하지 않는 기존의 알고리즘에 비하여 평균 응답시간은 약 9%, 스위치 상의 평균 대기패킷수는 21.6% 정토 향상시킨다는 것을 보여준다

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References

  1. T. Fen, 'A Survey of Interconnection Networks,' IEEE Computer, Dec., 1981 https://doi.org/10.1109/C-M.1981.220290
  2. P. T. Gaughan and S. Yalamanchili, 'Adaptive Routing Protocols for Hypercube Interconnection Networks,' IEEE Computer, Vol.26, No.5, pp.12-23, May, 1993 https://doi.org/10.1109/2.211888
  3. S. M. Mahmud, 'Performance Analysis Of Multilevel Bus Networks For Hierarchical Multiprocessors,' IEEE Trans. on Computers, Vol.43, No.7, pp.789-805, Jul., 1994 https://doi.org/10.1109/12.293258
  4. L. K. John and Y. Liu, 'Performance Model for a Prioritized Multiple-Bus Multiprocessor System,' IEEE Trans. on Computers, Vol.45, No.5, pp.580-588, May, 1996 https://doi.org/10.1109/12.509909
  5. A. K. Kanda, 'Design and Analysis of Cache Coherent Multistage Interconnection Networks,' IEEE Trans. on Computers, Vol.42, No.4, pp.458-470, Apr., 1993 https://doi.org/10.1109/12.214692
  6. D. P. Agrawal, 'Graph Theoretical Analysis and Design of Multistage Interconnection Networks,' IEEE Trans. on Computers, Vol.C-32, No.7, pp.637-648, Jul., 1983 https://doi.org/10.1109/TC.1983.1676295
  7. L. N. Bhuyan, R. R. Iyer, T. Askar, A. K. Nanda, and M. Kumar, 'Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor,' IEEE Trans. on Parallel and Distributed Systems, Vol.8, No.1, pp.82-95, Jan., 1997 https://doi.org/10.1109/71.569657
  8. L. N. Bhuyan, A. K. Kanda, and T. Askar, 'Performance and Reliability of the Multistage Bus Networks,' Proc. of the Int'l. Conf. on Parallel Processing, pp.26-33, Aug., 1994 https://doi.org/10.1109/ICPP.1994.158
  9. J. Protic, M. Tomasevic, and V. Milutinovic, 'Distributed Shared Memory : Concepts and Systems,' IEEE Parallel & Distributed Technology, Vol.4, No.2, pp.63-79, Summer, 1996 https://doi.org/10.1109/88.494605
  10. M. stumm and S. Zhou, 'Algorithms Implementing Distributed Shared Memory,' IEEE Computer, Vol.23, No.5, pp. 54-64, May, 1990 https://doi.org/10.1109/2.53355
  11. G. S. Almasi and A. Gottlieb, 'Highly Parallel Computing,' 2nd Ed., Benjamin/Cummings Pub. Co., 1994
  12. S. Chen, J. A. Stankovic, F. Kurose, and D. Towsley, 'Performance Evaluation of Two New Disk Scheduling Algorithms for Real-Time System,' Journal of Real-Time Systems, Vol.3, pp.307-336, Sept., 1991 https://doi.org/10.1007/BF00364960