Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Tapered Etching of Field Oxide with Various Angle using TEOS

다양한 기울기를 갖는 TEOS 필드 산화막의 경사식각

  • 김상기 (한국전자통신연구부 집적회로연구부) ;
  • 박일용 (한국전자통신연구부 집적회로연구부) ;
  • 구진근 (한국전자통신연구부 집적회로연구부) ;
  • 김종대 (한국전자통신연구부 집적회로연구부)
  • Published : 2002.10.01
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Abstract

Linearly graded profiles on the field area oxide are frequently used in power integrated circuits to reduce the surface electric field when power devices are operated in forward or reverse blocking modes. It is shown here that tapered windows can be made using the difference of etch rates between the bottom and the top layer of TEOS film. Annealed TEOS films are etched at a lower rate than the TEOS film without annealing Process. The fast etching layer results in window walls having slopes in the range of 25$^{\circ}$∼ 80$^{\circ}$ with respect to the wafer surface. Taper etching technique by annealing the TEOS film applies to high voltage LDMOS, which is compatible with CMOS process, due to the minimum changes in both of design rules and thermal budget.

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References

  1. Semiconductor Integrated Circuit Processing Technology W. R. Runyan;K. E. Bean
  2. VLSI Technology S. M. Sze
  3. Lattice Silicon Processing for the VLSI Era S. Wolf
  4. ETRI Journal v.24 no.3 Characterization of via etch in CHF₃/CF₄ magnetically enhanced relative ion etching using neural networks S. K. Kwon;K. H. Kwon;B. W. Kim;J. M. Park;S. W. Yoo;K. S. Park;Y. K. Bae;B. W. Kim
  5. 전기전자재료학회논문지 v.15 no.1 Via Contact 형성을 위한 산화막 식각 공정의 신경망 모델 박종문;권성구;박건식;유성욱;배윤규;김변환;권광호
  6. 전기전자재료학회논문지 v.16 no.2 유도결합 플라즈마를 이용한 YMnO₃ 박막의 건식식각 특성 연구 민병준;김창일;장의구
  7. 전기전자재료학회논문지 v.14 no.2 단결정 6H-SiC 광전화학 습식식각에 대한 연구 송정균;정두찬;신무환
  8. IEEE Trans. on ED v.17 no.11 Failure analisis of evaporated metal interconnections at contact window Takayuki Yanagawa;Isao Takekoshi https://doi.org/10.1109/T-ED.1970.17108
  9. IEEE Trans. on ED v.25 no.7 Tapered windows in phosphorus-doped SiO₂ by ion implantation Janes C. North;Thomas E. McGahph;D. W. Rise;A. C. Adams https://doi.org/10.1109/T-ED.1978.19175
  10. EDL v.16 no.9 Breakdown voltage enhancement of the p-n junction by self-aligned double diffusion process through a tapered SiO2 implant mask H. S. Kim;S. D. Kim;M. K. Han;S. K. Yoon;Y. I. Choi https://doi.org/10.1109/55.406803
  11. IEEE Trans. on ED v.48 no.6 High-voltage power integrated circuit technology using SOI for driving plasma display panels J. Kim;T. M. Rho;S. G. Kim;Q. S. Song;D. W. Lee;J. G. Koo;K. I. Cho https://doi.org/10.1109/16.925257
  12. IEEE Trans. on ED v.46 no.9 Improvement on p-channel SOI LDMOS transistor by adaping a new tapered oxide technique Jongdae Kim;Sang-Gi Kim;Q. Sang Yong Lee;Jin Gun Koo;Dong Sung Ma https://doi.org/10.1109/16.784190
  13. Jpn. J. Appl. Phys. v.3 no.7 Redistribution of diffused boron in silicon by thermal oxidation T. Kato;Y. Nishi https://doi.org/10.1143/JJAP.3.377