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기계화학적 연마를 이용한 트렌치 구조의 산화막 평탄화

Oxide Planarization of Trench Structure using Chemical Mechanical Polishing(CMP)

  • 발행 : 2002.10.01

초록

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

키워드

참고문헌

  1. Microelectron. Reliability v.38 no.2 STI process steps for sub-quarter micron CMOS P. Sallagoity;F. Gaillard;M. Rivoire;M. Paoli;F. Martin https://doi.org/10.1016/S0026-2714(97)00166-2
  2. Solid state Device and Materials A post gigabit generation flash memory shallow trench isolation shceme, the LATI-STI process using 100% CMP planarization S. Deleonibus;M. Heitzmanny;Y. Gobil;F. Martin
  3. Chemical Mechanical Planarization of Microelectronic Materials J. M. Steigerwald;S. P. Murarka;R. J. Gutmann
  4. Journal of Materials Science : Materials in Electronics v.12 no.7 Optimization of post-CMP cleaning process for elimination of CMP slurry induced metallic contaminations Y. J. Seo;W. S. Lee;S. Y. Kim;J. S. Park;E. G. Chang https://doi.org/10.1023/A:1011242900843
  5. Solid State Technology CMP dishing effets in shallow trench isolation K. Smekalin
  6. 전기전자재료학회논문지 v.13 no.2 실리콘 웨이퍼 위에 증착된 실리케이트 산화막의 CMP 슬러리 오염 특성 김상용;서용진;이우선;장의구
  7. 전기전자재료학회논문지 v.14 no.1 STI-CMP 공정에서 Torn oxide 결함 해결에 관한 연구 서용진;정헌상;김상용;이우선;이강현;장의구
  8. 전기전자재료학회논문지 v.14 no.7 CMP 공정에서 마이크로 스크래치 감소를 위한 슬러리 필터의 특성 김철복;김상용;서용진
  9. Proceedings of VLSI Multilevel Interconnection Conference Two-step SOG etchback technique to control IMD planarization for the severe DRAM topography L. J. Chen