A Study on sub 0.1$\mu\textrm{m}$ ULSI Device Quality Using Novel Titanium Silicide Formation Process & STI

새로운 티타늅 실리사이드 형성공정과 STI를 이용한 서브 0,1$\mu\textrm{m}$ ULSI급 소자의 특성연구

  • 엄금용 (성남기능대학 광전자과) ;
  • 오환술 (건국대학교 전자·정보통신 공학과)
  • Published : 2002.05.01

Abstract

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

Keywords

References

  1. J. U. Bae et al., 'Effect of Pre-Amorphization of Polycrystalline on Agglomeration of $TiSi_2$ in subquarter micron si lines,' J. of Applied Physics Vol. 86, No. 9, pp. 4943-4947, 1 November 2000 https://doi.org/10.1063/1.371523
  2. T. Yamaguchi et al., 'Effect of Plasma-Induced damage on interfacial Reductions of Titanium Thin Films on Silicon Surfaces', A Physics Letters, Vol. 76, No. 17, pp. 2353-2356, April 2000 https://doi.org/10.1063/1.126345
  3. S. Santucci et al., 'X-ray Reflectivity Study on Tin/Ti/Si Structures before and after Annealing', Thin Solid Films, Vol. 360, pp. 89-95, 2000 https://doi.org/10.1016/S0040-6090(99)00891-3
  4. 엄금용, 오환술, 'MOS 구조에서의 얇은 산화막에 대한 절연특성에 관한연구', 건국대학교 학술지, 제41집, 제2호, pp. 79-89, ]une(l997)
  5. Ernest et al., 'Ultra-thin Oxide Reliability for ULSI Applications', Semiconductor Science Technology Vol. 15, pp. 425-435, 14 March 2000 https://doi.org/10.1088/0268-1242/15/5/301
  6. Coming Chen et al., 'Shallow-Trench Isolation with Raised Field-Oxides Structure', Jpn. A Applied Physics, Vol. 39, No. 3A, pp. 1080-1084, March 2000 https://doi.org/10.1143/JJAP.39.1080
  7. Toshiyuki oishi et al., 'Isolation Edge Effect Depending on Gate Length of MOSFET's with Various Isolation Structures,' IEEE Transaction on Electron Devices, Vol. 47, No. 4, pp. 822-827, April 2000 https://doi.org/10.1109/16.830999
  8. S. L. Cheng et al., 'Effects of Stress on the Growth of TiSi2 Thin Films on (001) Si, Applied Physics Letters, Vol. 14, No. 10, pp. 1406-1408, 8 March 1999 https://doi.org/10.1063/1.123565
  9. Jeffrey Lutze et al., 'Transistor Off-State Leakage Current Induced by $TiSi_2$ Pre-Amorphizing Implant in a $0.2{\mu}m$ CMOS Process', IEEE Transaction on Electron Devices, Vol. 21, No. 4, pp. 155-157, April 2000 https://doi.org/10.1109/55.830966
  10. Wei JL et al., 'Stress-induced High Field Gate Leakage Current Ultra-Thin Gate Oxide', Elsevier Science Ltd., pp. 977-980, 1 June 2000
  11. Shih-Chia Lin et al., 'A Closed-Form Back Gate-Bias Related Inverse Narrow-Channel Effect Model for Deep-Submicron VLSI CMOS Device using Shallow Trench Isolation', IEEE Transaction on Electron Devices, Vol. 47, No. 4, p. 725, April 2000 https://doi.org/10.1109/16.830986
  12. 엄금용, 오환술, '개선된 티타늄 실리사이드 형성 방법을 이용한 서브 $0.1{\mu}$ 게이트 산화막의 특성 개선에 관한연구', 한국물리학회, 새물리 제41권, 제3호, pp.182-186, September(2000)
  13. Zhigang wang et al., 'Effect of Polysilicon Gate Type on The Flatband Voltage Shift for Ultrathin Oxide-Nitride Gate Stacks', IEEE Electron Devices Letters, Vol. 21, No. 4, pp. 170-172, April 2000 https://doi.org/10.1109/55.830971
  14. Koji Eriguchi et al., 'Effects of Strained Layer near Interface on Electrical Characteristics of Ultra-thin Gate Oxides' J. of Applied Physics, Vol. 87, No. 4, pp. 1990-1995, 15 February 2000 https://doi.org/10.1063/1.372125
  15. Dong Kyun Sohn et al., 'Reduction of Leakage Current for Shallow n+/p Junction Fabricated Using C49 $TiSi_2$ as a Diffusion Source', J. of The Electro chemical Society, Vol. 146, No. 10, pp. 3837-3842, 2 June 1999 https://doi.org/10.1149/1.1392561
  16. J. Sune et al., 'Are Soft Breakdown and Hard Breakdown of Ultrathin Gate Oxide Actually Different Failire Mechanisms' IEEE Electron Device Letters, Vol. 21, No. 4, pp. 167-169, April 2000 https://doi.org/10.1109/55.830970
  17. P. T. Lai et al., 'Interface Properties of NO-Annealed $N_2O$ Grown Oxynitride' IEEE Transaction on Electron Devices, Vol. 46, No. 12, pp. 2311-2314, December 1999 https://doi.org/10.1109/16.808070