Design and implementation of low-power VLSI system using software control of supply voltages

소프트웨어 전압 제어를 사용한 저전력 VLSI 시스템의 설계 및 구현

  • 이성수 (이화여자대학교 과학기술대학교 정보통신학과)
  • Published : 2002.04.01

Abstract

In this paper, a novel low-power VLSI system architecture was proposed. By exploiting software control of supply voltages, it simplifies hardware implementation, reduces power consumption efficiently, and avoids complicated interface circuits. The proposed architecture models clock frequency-supply voltage relationship by software modelling, enables individual control of supply voltages for all chips in the system, and restricts clock frequency to discrete levels of $f_{CLK}$, $f_{CLK}$2, $f_{CLK}$3... where $f_{CLK}$ is the master clock frequency A prototype system was implemented by modifying off-the-shelf microprocessor evaluation board and adding simple discrete devices such as level shifters and voltage switches. It was measured that the power consumption was reduced from 0.58W to 0.12W in the Prototype system. system.

본 논문에서는 공급 전압을 순수하게 소프트웨어적으로 제어함으로서, 하드웨어 구현이 간단하고 전력 소모를 효과적으로 줄이며 복잡한 인터페이스 회로가 필요 없는 새로운 저전력 VLSI 시스템 아키텍처를 제안하였다. 제안된 아키텍처는 클록 주파수-공급 전압 특성을 순수하게 소프트웨어적으로만 모델링하고, 시스템상의 여러 칩들에 대해서 각각 독립적으로 공급 전압을 제어하고, 주 클록 주파수 f/sub CLK/의 1/n인 f/sub CLK/, f/sub CLK/2, f/sub CLK/3...만을 클록 주파수로 허용하였다. 또한, 제안된 저전력 VLSI 시스템 아키텍처의 프로토타입 시스템을 제작하고 전력 소모를 측정하였다. 프로토타입 시스템은 기존의 상용 마이크로프로세서 평가 보드를 약간 수정하여 레벨 쉬프터와 전안 스위치와 같은 간단한 개별 소자만을 덧붙여서 제작되었으며, 0.58W이던 전력 소모가 0.12W로 감소함을 확인할 수 있었다.

Keywords

References

  1. J. Rabaey, 'Low-power silicon architectures for wireless commnications,' Proceedings of Asia and South Pacific Design Automation Conference, pp. 379-380, 2000 https://doi.org/10.1109/ASPDAC.2000.835128
  2. M. Srivastava, A. Chandrakasan, and R. Brodersen, 'Predictive system shutdown and other architectural techniques for energy efficient programmble computation,' IEEE Transactions on VLSI Systems, Vol. 4, No. 1, pp. 42-55, Mar. 1996 https://doi.org/10.1109/92.486080
  3. A. Chandrakasan and R. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995
  4. F. Yao, A. Demers, and S. Shenker, 'A scheduling model for reduced CPU energy,' Proceedings of IEEE Annual Foundations of Computer Science, pp. 374-382, 1995 https://doi.org/10.1109/SFCS.1995.492493
  5. T. Ishihara and H. Yasuura, 'Voltage scheduling problem for dynamically variable voltage processors,' Proceedings of IEEE International Symposium on Low Power Electronics and Design, pp. 197-202, 1998
  6. Y. Shin and K. Choi, 'Power conscious fixed priority scheduling for hard real-time systems,' Proceedings of Design Automation Conference, pp. 134-139, 1999 https://doi.org/10.1145/309847.309901
  7. I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. Srivastava, 'Power optimization of variable-voltage core-based systems,' IEEE Transactions on Computer-Aided Design of Integrated Curciuts and Systems, Vol. 18, No. 12, pp. 1702-1714, Dec. 1999 https://doi.org/10.1109/43.811318
  8. S. Lee and T. Sakurai, 'Run-time voltage hopping for low-power real-time systems,' Proceedings of Design Automation Conference, pp. 806-809, 2000 https://doi.org/10.1109/DAC.2000.855424
  9. D. Shin, J. Kim, and S. Lee, 'Intra-task voltage scheduling for low energy hard real-time applications,' IEEE Design and Test of Computers, Vol. 18, No. 2, pp. 20-30, Mar. 2001 https://doi.org/10.1109/54.914596
  10. T. Burd, T. Pering, A. Stratakos, and R. Brodersen, 'A dynamic voltage scaled microprocessor system,' Proceedings of IEEE International Solid-State Circuits Conference, pp. 294-295, 2000
  11. V. Gutnik and A. Chandrakasan, 'An efficient controller for variable supply-voltage low power processing,' Proceedings of IEEE Symposium on VLSI Circuits, pp. 158-159, 1996 https://doi.org/10.1109/VLSIC.1996.507753
  12. A. Chandrakasan, S. Sheng, and R. Brodersen, 'Low-power CMOS digital design,' IEEE Journal of Solid State Circuits, Vol. 27, No. 4, pp. 473-484, Apr. 1992 https://doi.org/10.1109/4.126534
  13. T. Sakurai and A. Newton, 'Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas,' IEEE Journal of Solid State Circuits, Vol. 25, No. 2, pp. 584-594, Apr. 1990 https://doi.org/10.1109/4.52187
  14. ISO-IEC JTC1/SC29/WG11 14496-2, 'Coding of audio-visual objects: visual,' Oct. 1998