대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

부분 채널도핑된 GaAs계 이중이종접합 전력FET의 선형성 증가

Linearity Enhancement of Partially Doped Channel GaAs-based Double Heterostructure Power FETs

  • 김우석 (포항공과대학교 전자전기공학과) ;
  • 김상섭 (포항공과대학교 전자전기공학과) ;
  • 정윤하 (포항공과대학교 전자전기공학과)
  • Kim, U-Seok (Dept. of Electronic Electrical Engineering, Pohang University of Science and Technology) ;
  • Kim, Sang-Seop (Dept. of Electronic Electrical Engineering, Pohang University of Science and Technology) ;
  • Jeong, Yun-Ha (Dept. of Electronic Electrical Engineering, Pohang University of Science and Technology)
  • 발행 : 2002.01.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

HFET 소자의 선형성과 게이트-트레인 항복특성을 향상시키기 위해 부분채널 도핑된 Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.25/Ga/sub 0.75/As/Al/sub 0.25/Ga/sub 0.75/As 이종접합 구조를 갖는 FET를 제안하였다. 제안된 HFET는 게이트 전극 아래로 도핑되지 않은 AlGaAs 진성공급층을 두어 -2OV 의 높은 항복전압을 얻었다. 또한 소자의 InGaAs 채널에 부분 도핑을 실시하여, 균일 채널 도핑을 실시한 경우보다 향상된 선형성을 유도하였고, 2차원 전산모사 견과와 제작 및 측정결과를 통해 선형성의 향상을 확인하였다. 본 실험에서 제안된 HFET소자는 DC측정 결과와 고주파측정 결과 모두에서 기존의 FET소자들에 비해 향상된 선형성을 나타내었다.

To increase the device linearities and the breakdown-voltages of FETs, $Al_{0.25}$G $a_{0.75}$As/I $n_{0.25}$G $a_{0.75}$As/A $l_{0.25}$G $a_{0.75}$As partially doped channel FET(DCFET) structures are proposed. The metal insulator-semiconductor(MIS) like structures show the high gate-drain breakdown voltage(-20V) and high linearities. We propose a partially doped channel structure to enhance the device linearity to the homogeneously doped channel structure. The physics of partially doped channel structure is investigated with 2D device simulation. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range. bias range.

키워드

참고문헌

  1. P. Robiin, L. Rice, S. B. Bibyk, and H. Morkoc, 'Nonlinear parasitics in MODFET's and MODFET I-V Characteristics', IEEE Trans. Electron Devices, Vol. 35, p. 1207, 1988 https://doi.org/10.1109/16.2539
  2. Y. J. Chan and M. T. Yang, 'Device Linearity Improvement by AlGaAs/lnGaAs Heterostructure Doped - Channel FET's', IEEE Electron Device Lett' , Vol 16, No. 1, p. 33-35, January 1995 https://doi.org/10.1109/55.363208
  3. M. T. Yang and Y. J. Chan, 'Device Linearity Comparisions Between Doped Channel and Modulation Doped Design in Pseudomorphic AlGaAs/lnGaAs Hetero structure', IEEE Trans. Electron Devices, Vol. 43, No. 8, p. 1174-1180, 1996 https://doi.org/10.1109/16.506765
  4. J. Dickrnann, C. Woelk, A Schurr, E. Kohn, and P. Narozny, 'Determination of the optimum condition to Introduce the Doping in the Channel of High Speed Doped Channel AlGaAs/lnGaAs HFET's', High Speed Semiconductor Devices and Circuits, 1991., Proceedings IEEE/Cornell Conference on Advanced Concepts , p. 208-217, 1991