Communications of the Korean Institute of Information Scientists and Engineers (정보과학회지)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지

저전력 온칩 메모리에 관한 연구 동향 및 개발 방향

  • Published : 2002.10.01
Download PDF
⟨ Previous Next ⟩

Abstract

Keywords

References

  1. Proc. Hot Chips 8 StrongARM SA110, a 160mhz 32b 0.5w COS ARM processor S. Santhanm
  2. Technical report UPC-DAC-1997-28 Static Locality Analysis for Cache Management F. J. Sanchez;A. Gonzalez;M. Valero
  3. ACM Computing Surveys v.14 no.3 Cache Memories A. J. Smith
  4. Proc. the 32rd Intl. Symp. on Computer Architecture High-bandwidth Address Translation for Multiple-issue Processors T. M. Austin;G. S. Sohi
  5. Proc. the 19th Intl. Symp. on Computer Architecture Tradeoffs in Supporting Two Page Sizes M. Talluri;S. Kong;M. D. Hill;D. A. Patterson
  6. Proc. the 4th Workshop on Workstation Operating Systems Virtual Memory Support for Multiple Page Sizes Y. A. Khalidi
  7. Proc. Intl. Symp. on Low Power Electronics and Design Reducing TLB Power Requirements T. Juan;T. Lang;J. Navarror
  8. IEEE Journal of Solid State Circuits v.28 no.1 Trading Speed for Low Power by Choice of Supply and Threshold Voltages D. Liu;C. Svensson
  9. Proc. Power Driven Microarchitecture Workshop, attached to ISCA98 Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System T. Pering;T.Burd;R. Brodersen
  10. Proc. the 10th Intl. conf. on VLSI Design Energy-Efficiency of VLSI Cache: A Comparative Study M. B. Kamble;K. Ghose
  11. Proc. Intl. Symp. on Low Power Electronics and Design Analytical Energy Dissipation Models for Low Power Caches M. B. Kamble;K. Ghose
  12. Proc. Intl. Symp. on Low Power Electronics and Design Reducing Power in Superscalar Processor Caches using Subbanking, Multiple Line Buffers and Bit-line Segmentation K. Ghose;M. B. Kamble
  13. IEEE Transactions on Computers v.49 no.1 Filtering Memory References to Increase Energy Efficiency Kin(et al.)
  14. Univ. of Colorado Technical Report Low Power TLB Design for HIgh Performance Microprocessors S. Manne;A. Klauser;D. Grunwald;F. Somenzi