The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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A Study on the Design of Highly Parallel Multiplier using VCGM

VCGM를 사용한 고속병렬 승산기 설계에 관한 연구

  • Published : 2002.06.01
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Abstract

In this paper, a new designed circuit of highly parallel multiplier using standard basis over $GF(2^m)$ is presented. Prior to construct the multiplier circuit, we provide the Vector Code Generate Module(VCGM) that generate each vector codes for multiplication. Using these VCGMs, we can get all vector codes necessary for operation and modular sum up each independent corresponding basis, respectively. Following the equations in this paper, we can design generalized multiplier to m. For the proposed circuit in this parer, we show the example in $GF(2^4)$ using VCGMs. In this paper, we build a multiplier with VCGMs, AND blocks, and EX-OR blocks. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer then other circuit. We verify the proposed circuit by functional simulation and show its result. Finally, we compare the circuit composition with other works and show its result with a table.

본 논문에서는 GF($2^{m}$)상의 표준기저를 사용한 새로운 형태의 고속병렬 승산회로를 제안하였다. 승산회로의 구성에 앞서, 연산에 필요한 벡터코드들을 생성하는 벡터코드생성모듈(VCGM)을 제안하였다. 이를 통해 연산에 필요한 모든 벡터코드들을 찾을 수 있으며 이들로부터 기저들간의 독립된 모듈러 가산을 취해 승산이 이루어지도록 하였다. 이러한 과정을 수식을 통해 보임으로써, m에 대한 일반화된 회로의 설계가 가능하도록 하였으며, 간단한 형태의 승산회로구성의 예를 GF($2^4$)를 통해 보였다. 본 논문에서 제안된 승산회로는 그 구성이 VCGM, AND 블록, EX-OR 블럭을 통해 이루어짐으로 m에 대한 확장이 용이하며 VLSI에 유리하다. 또한, 회로내부에 메모리 소자를 사용하지 않고, 연산과정 중 소자에 의해 발생하는 지연시간이 적으므로 고속의 연산을 수행할 수 있다. 제안된 회로의 연산동작을 시뮬레이션을 통해 검증하였으며, 참고문헌의 승산기와 그 구성을 비교하였다.

Keywords

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