한국초전도ㆍ저온공학회논문지 (Progress in Superconductivity and Cryogenics)

  • 제4권1호
  • /
  • Pages.35-39
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  • 2002
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  • 1229-3008(pISSN)
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  • 2287-6251(eISSN)
한국초전도저온학회 (The Korean Society of Superconductivity and Cryogenics)
권호 표지

단자속 양자 AND gate의 시뮬레이션과 Mask Drawing

Simulation and Mask Drawing of Single Flux Quantum AND gate

  • 발행 : 2002.05.01
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초록

We have simulated and laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. SFQ AND gate circuit is a combination of two D Flip-Flop. D Flip-Flop and dc SQUID are the similar shape form the fact that it has the loop inductor and two Josephson junction We obtained perating margins and accomplished layout of the AND gate. We got the margin of $\pm$38%. over. After layout, we drew mask for fabrication of SFQ AND sate. This mask was included AND gate, dcsfq, sfqdc, rs flip-flop and jtl.

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참고문헌

  1. IEEE Trans. Appl. Supercond v.1 RSFQ Logic/Memory Family: A new Josephoson-Junction Technology for Sub-Terahertz Clock-Frequency Digital Systems K. K. Likarev;V.K. Semenov
  2. IEEE Trans. Appl. Supercond. v.9 Case Study in RSFQ design: Fast Pipelined Parallel Adder P. Bunyk;P. Litskevitch
  3. IEEE Trans. Appl. Supercond. v.11 RSFQ Time Digitizing System Alex F. Kirichenko;Saad Sarwana, Oleg A.;Mukhanov, Igor V. Vernik
  4. IEEE Trans. Appl. Supercond. v.9 High-frequency Clock Operation of Josephson 256-word x 16-bit RAMs Shuichi Nagasawa;Hideaki Numata;Yoshihito Hashimoto;Shuichi Tahara
  5. IEEE Trans. Appl. Supercond. v.11 On-Chip High-Frequency Diagnostic of RSFQ Logic Cells Pascal Febvre;Jean-Claude Berthet;David Ney;Agnes Roussy;Jun Wu Tao;Gilbert Angenieux https://doi.org/10.1109/77.919339
  6. Niobium Design Rules HYPRES