References
- S. B. Wicker, Error Control Systems for Digital Communication and Storage, Upper Saddle River, NJ:Prentice-Hall, 1995
- F. Braun and M. Waldvogel, 'Fast incremental CRC updates for IP over ATM networks,' in Proc. IEEE Workshop on High Performance Switching and Routing, pp. 48-52, 2001 https://doi.org/10.1109/HPSR.2001.923602
- J. Cai and C. W. Chen, 'Video streaming: An FEC-based novel approach,' in Proc. Canadian Conf. Elec. and Comp. Eng., vol. 1, pp. 613-618, 2001 https://doi.org/10.1109/CCECE.2001.933754
- Z. Cao, Z. Wang, and E. Zegura, 'Performance of hasing-based schemes for internet load balancing,' in Proc. 2000 IEEE INFOCOM, vol. 1, pp. 332-341, 2001
- R. Anand, K. Ramchandran, and I. V. Kozintsev, 'Continuous error detection for reliable communications,' IEEE Trans. Commun., vol. 49, no. 9, pp. 1540-1549, Sept. 2001 https://doi.org/10.1109/26.950341
- A. J. McAuley, 'Weighted sum codes for error detection and their comparison with existing codes,' IEEE/ACM Trans. Networking, vol. 2, no. 1, pp. 16-22, Feb. 1994 https://doi.org/10.1109/90.282604
- D. C. Feldmeier, 'Fast software implementation of error detection codes,' IEEE/ACM Trans. Networking, vol. 3, no. 6, pp. 640-651, Dec. 1995 https://doi.org/10.1109/90.477710
- R. Nair, G. Ryan, and F. Farzaneh, 'A symbol based algorithm for hardware implementation of cyclic redundancy check,' in Proc. 1997 VHDL Int. Users' Forum, pp. 82-87 https://doi.org/10.1109/VIUF.1997.623934
- T. Kasami, 'A decoding procedure for multiple- error- correcting cyclic codes,' IEEE Trans. Inform. Theory, vol. 10, pp. 134-138, 1964 https://doi.org/10.1109/TIT.1964.1053649
- F. J. MacWilliams and N. J. A. Sloane, The Theory of Error Correcting Codes, North-Holland, New York, 1977
- I. B. Pyne and E. J. McCluskey, Jr., 'The reduction of redundancy in solving prime implicant tables,' IEEE Trans. Electronic Computers, vol. 11, pp. 473-482, 1962 https://doi.org/10.1109/TEC.1962.5219386