대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

듀얼 위상 주파수 검출기를 이용한 차지펌프 PLL 설계

Design of the Charge pump PLL using Dual PFD

  • 이준호 (LG電子) ;
  • 이근호 (群山大學校 電子情報工學部) ;
  • 손주호 (全北大學校 電氣電子工學科) ;
  • 김선홍 (全北大學校 電氣電子工學科) ;
  • 유영규 ((주)플레넷 中央硏究所) ;
  • 김동용 (全北大學校 電氣電子工學科)
  • Lee, Jun-Ho (LG Electronics) ;
  • Lee, Geun-Ho (Kunsan National University, School of Electronic & Information Engineering) ;
  • Son, Ju-Ho (Dept. of Electrical Engineering, Chonbuk National University) ;
  • Kim, Sun-Hong (Dept. of Electrical Engineering, Chonbuk National University) ;
  • Yu, Young-Gyu (PLANET System) ;
  • Kim, Dong-Yong (Dept. of Electrical Engineering, Chonbuk National University)
  • 발행 : 2001.08.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 위상획득과정과 동기과정에서의 trade-off를 향상시킨 듀얼 위상 주파수 검출기를 이용하여 차지펌프 PLL을 설계하였다. 제안된 듀얼 위상 주파수 검출기는 상승에지에서 동작하는 POSITIVE 위상 주파수 검출기와 하강에지에서 동작하는 NEGATIVE 위상 주파수 검출기로 구성되어있다. 또한 PLL에 사용된 차지펌프는 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, reference spurs와 전압제어발진기의 변동을 감소시킬수 있도록 구현하였다. 제안된 PLL의 동작특성은 0.25${\mu}m$ CMOS 공종 파라미터를 이용하여 SPICE 시뮬레이션을 통해 검증되었다.

In this paper, the charge pump PLL using the dual PFD to improve the trade-off between acquisition behavior and locked behavior is proposed. This dual PFD consists of a positive edge triggered PFD and a negative edge triggered PFD. The proposed charge pump shows that it is possible to overcome the issue of the charge pump current imsmatch by the current subtraction circuit. Also, this charge pump can suppress reference spurs and disturbance of the VCO control voltage. The proposed charge pump PLL is simulated by SPICE using 0.25${\mu}m$ CMOS process parameters.

키워드

참고문헌

  1. M. Soyuer and R. G. Meyer, 'Frequency Limitations of a Conventional Phase-Frequency Detector,' IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 1019-1022, Aug. 1990 https://doi.org/10.1109/4.58298
  2. F. M. Gardner, 'Charge-Pump Phase-Lock Loops,' IEEE Trans. Comm., vol. COM-28, pp. 1849-1858, Nov. 1980 https://doi.org/10.1109/TCOM.1980.1094619
  3. K. M. Ware, H.-S. Lee, and C. G. Sodini, 'A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors,' IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1560-1568, Dec. 1989 https://doi.org/10.1109/4.44991
  4. Y. Sumi, S. Obote, N. Kitai, R. Furuhashi, H. Ishii, Y. Matsuda, and Y. Fukui, 'Dead-zone-less PLL Frequency Synthesizer by Hybrid Phase Detectors,' in Proc. IEEE ISCAS, vol. 4, pp. 410-414, July 1999 https://doi.org/10.1109/ISCAS.1999.780029
  5. M. G. Degrauwe, J. Rijmenants, E. A. Vittoz, and H. J. D. Man, 'Adaptive Biasing CMOS Amplifiers,' IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 522-528, June 1982 https://doi.org/10.1109/JSSC.1982.1051769
  6. Y. Sugimoto and T. Ueno, 'The Design of a 1V, 1GHz CMOS VCO Circuit with In-phase and Quadrature-phase Outputs,' in Proc. IEEE ISCAS, vol. 1, pp. 269-272, June 1997 https://doi.org/10.1109/ISCAS.1997.608698
  7. P.-C. Yu and J.-C. Wu, 'A Fully Integrated 3.3V 1-600 MHz CMOS Frequency Synthesizer,' in Proc. IEEE ISCAS, vol. 3, pp. 1828-1831, June 1997 https://doi.org/10.1109/ISCAS.1997.621502
  8. W. F. Egan, Frequency Synthesis by Phase Lock, Second Edition, John Wiley & Sons, 2000