Antifuse Circuits and Their Applicatoins to Post-Package of DRAMs

  • Wee, Jae-Kyung (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.) ;
  • Kook, Jeong-Hoon (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.) ;
  • Kim, Se-Jun (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.) ;
  • Hong, Sang-Hoon (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.) ;
  • Ahn, Jin-Hong (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.)
  • 발행 : 2001.12.01

초록

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

키워드

참고문헌

  1. K. Nagata, T. Matano, K. Sakakibara, K. Miyano, Y. Hoshino, S. Isa, and S. Nakazawa, '256Mbit Synchronous DRAM,' NEC Research & Development, vol. 38, no. 1, pp. 1-8, Jan. 1993
  2. J. Bernstein, Y. Hua, and W. Zhang, 'Laser Energy Limitation for Buried Metal Cuts,' IEEE Elec. Dev. Letters, vol. 19, no. 1, pp. 4-6, Jan. 1998 https://doi.org/10.1109/55.650334
  3. W. Zhang, J.-H. Lee, and J. B. Bernstein, 'Energy Effect of Laser-Induced Vertical Metallic Link,' IEEE Trans. on. Semiconductor Manufacturing, vol. 14, no. 2, pp. 163-169, May 2001 https://doi.org/10.1109/66.920728
  4. M. Alavi, M. Bohr, J. Hicks, M. Denham, A. Cassens, D. Douglas, and M. C. Tsai, 'A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process,' IEDM Technical Digest, pp 855-858, Dec. 1997 https://doi.org/10.1109/IEDM.1997.650515
  5. G. Zhang, C. Hu, P. Yu, S. Chiang, and E. Hamdy, 'Metal-to-Metal Antifuses with Very Thin Silicon Dioxide Films,' IEEE Elec. Dev. Letters, vol. 15, no. 8, pp 310-312, Aug. 1994 https://doi.org/10.1109/55.296226
  6. David J. Pilling, et al., 'Circuits for Improving The Reliability of Antifuses in Integrated Circuits,' U.S. patent number 5680360, Oct. 1997
  7. T. Takahashi, et al., 'A Multigigabit DRAM Technology with 6F2 Open-Bit Line Cell, Distributed Overdriven Sensing, and Stacked-Flash Fuse,' Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1721-1727, 2001 https://doi.org/10.1109/4.962294
  8. T. Hamamoto et al., 'A Skew and Jitter Suppress DLL Architecture for high frequency DDR SDRAMs', in Symp. VLSI Circuits Dig. Tech. Papers, June 2000, pp.76-77 https://doi.org/10.1109/VLSIC.2000.852857
  9. S. Kuge et al., 'A 0.18um 256Mb DDR-SDRAM with Low-Cost Post-Mold-Tuning Method for DLL Replica' in ISSCC Dig. Tech. Papers, Feb. 2000, pp 402-403 https://doi.org/10.1109/ISSCC.2000.839834
  10. Todd A. Merritt, et al., 'On-Chip Program Voltage Generator for Antifuse Repair,' U.S. patent number 5604693, Feb. 1997
  11. J. S. Choi, J. K. Wee, P. J. Kim, J. K. Oh, C. H. Lee, H. Y. Cho, J. Y. Chung S. C. Kim, and W. Yang, 'Antifuse EPROM Circuit for Field Programmable DRAM,' Int'l Solid-State Circuits Conference Digest of Technical Papers, pp.406-407, Feb. 2000 https://doi.org/10.1109/ISSCC.2000.839836
  12. J. Wee, W. Yang, E. Ryou, J. Choi, S. Ahn, J. Chung, and S. Kim, 'An antifuse EPROM circuitry scheme for field-programmable repair in DRAM,' in IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1408-1414, Oct. 2000 https://doi.org/10.1109/4.871316
  13. K. Min, J. Park, S. Lee, Y. Kim, T. Yang, J. Joo, K. Lee, J. Wee, and J. Chung, 'A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs,' in Symposium on VLSI circuits Digest of Technical Papers, pp. 67-68, in Kyoto, Japan, June 2001 https://doi.org/10.1109/4.982432
  14. H. Koike, et al, '30ns 64Mb DRAM with Built-in Self-Test and Repair Function', in IEEE Int'l Solid-State Circuit Conf., San Francisco, pp.150-152, Feb. 1992 https://doi.org/10.1109/4.165332
  15. K. Lim, and et al, 'Bit Line Coupling Scheme and Electrical Fuse Circuit For Relaible Operation of High Density DRAM,' in Symp. VLSI Circuits Dig. Tech. Papers, June 2001, pp.33-34 https://doi.org/10.1109/VLSIC.2001.934186
  16. G.J. Gastan, I.G. Daniels, 'Efficient extraction of metal parasitic capacitances', Proc. IEEE Conference on Microelectronic test Structures, vol. 8, pp. 157-160, Mar. 1995 https://doi.org/10.1109/ICMTS.1995.513964
  17. H. Samavati, A. Hajimiri, A. Shahani, G. Nasserbarkht, T. Lee, 'Fractical capacitors', Int'l Solid-State Circuits Conference Digest of Technical Papers, pp. 256-257, Feb. 1998
  18. J. Dickson, 'On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique,' in IEEE Journal of Solid-State Circuits, vol. 11, pp. 374-378, June 1976
  19. Y. Tsukikawa, T. Kajimoto, Y. Okasaka, Y. Morooka, K. Furutani, H. Miyamoto, and H. Ozaki, 'An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAM's,' in IEEE Journal of Solid-State Circuits, vol. 29, no. 4, pp. 534-538, April 1994
  20. D. J. Culter K. D. Beigel, 'Semiconductor Junction Antifuse circuit,' U.S. patent number 644, 232, May 1996