참고문헌
- R. E. Bryant, 'Graph-Based Algorithms for Boolean Function Manipulation,' IEEE Transactions On Computers, vol. 35, no. 8, pp. 677-691, Aug. 1986 https://doi.org/10.1109/TC.1986.1676819
- C. S. Wallace, 'A Suggestion for a Fast Multiplier,' IEEE Transactions On Electronic Computers, vol. 13, pp. 14-17, Feb. 1964 https://doi.org/10.1109/PGEC.1964.263829
- N. Takagi, H. Yasuura, and S. Yajima, 'High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree,' IEEE Transactions On Computers, vol. 34, no. 9, pp. 789-796, Sept. 1985 https://doi.org/10.1109/TC.1985.1676634
- F. J. Taylor, 'Large Moduli Multipliers for Signal Processing,' IEEE Transactions On Circuits and Systems, vol. 28, no. 7, pp. 731-736, July 1981 https://doi.org/10.1109/TCS.1981.1085027
- B. P. Sinha, and P. K. Srimani, 'Fast Parallel Algorithms for Binary multiplication and Their Implementation on Systolic Architectures,' IEEE Transactions On Computers, vol. 38, no. 3, pp. 424-431, Mar. 1989 https://doi.org/10.1109/12.21128
-
A. Hiasat, 'New Memoryless, mod (
$2^n{\pm}1$ ) Residue Multiplier,' Electronics Letters, vol. 28, no. 3, pp. 314-315, Jan. 1992 https://doi.org/10.1049/el:19920194 - A. A. Hiasat, 'New Efficient Structure for a Modular Multiplier for RNS,' IEEE Transactions On Computers, vol. 49, no. 2, pp. 170-174, Febr. 2000 https://doi.org/10.1109/12.833113
- E. D. Di Claudio, F. Piazza, and G. Orlandi, 'Fast Combinational Processors for DSP Applications,' IEEE Transactions On Computers, vol. 44, no. 5, pp. 624 -633, May 1995 https://doi.org/10.1109/12.381948
- A. Saed, M. Ahmadi, and G. A. Jullien, 'Analog Digits: Bit Level Redundancy in a Binary Multiplier,' IEL Data Base(0-7803-5148-7/98/$10.00c1998 IEEE), pp. 236-240, 1998 https://doi.org/10.1109/ACSSC.1998.750861
- J. B. Shin, J. K. Kim, and H. L. Kwang, 'Optimisation of Montgomery Modular Multiplication Algorithm for Systolic Arrays,' Electronics Letters, vol. 34, no. 19, pp. 1830-1831, Sept. 1998 https://doi.org/10.1049/el:19981299
-
C. Efstathiou, D. Nikolos, and J. Kalamatianos, 'Area-Time Efficient Modulo
$2^n-1$ Adder Design,' IEEE Transactions On Circuits and Systems-II: Analog and Digital Signal Processing, vol. 41, no. 7, pp. 463-467, July 1994 https://doi.org/10.1109/82.298378 - R. F. Coughlin and F. F. Driscoll, Operational-Amplifiers & Linear Integrated Circuits, Prentice Hall, pp. 434-436, 1998
- T. L. Floyd, Digital Logic Fundamentals, C. E. Merrill Publishing Company, pp. 205-212, 1977
- C. D. Walter, 'Systolic Modular Multiplication,' IEEE Transactions On Computers, vol. 42, no. 3, pp. 376 - 378, Mar. 1993 https://doi.org/10.1109/12.210181
- B. Arazi, 'Digital Signature Device,' US Patent, #5448639, 1995
- 김 광조, 김 철 '정보보호 이론의 발전,' 전자공학회지, 제 21권 5호, pp. 443-456, 1994년 5월