저전력 VLIW 명령어 추출을 위한 연산재배치 기법

Operation Rearrangement for Low-Power VLIW Instruction Fetches

  • 신동군 (서울대학교 컴퓨터공학부) ;
  • 김지홍 (서울대학교 컴퓨터공학부)
  • 발행 : 2001.10.01

초록

이동용 응용프로그램이 요구하는 계산량이 늘어남에 따라 많은 이동용 컴퓨터시스템이 성능을 높이기위해 VLIW 프로세서를 사용하여 설계되고 있다. VLIW 구조에서는 하나의 명령어(instruction)가 여러개의 연산(operation)을 가지고 있는데, 이들이 명령어안에서 어떻게 배치되는냐에 따라 명령어 추출(fetch)시의전력 소모가 큰 차이를 보인다. 본 논문에서는 저전력 VLIW 명령어 추출을 위해 컴파일어의 후단계로 사용되는 최적의 연산 재배치 기법을 제시한다. 제안된 방법은 연속적인 명령어 추출시의 스위칭 활동(switching activity)이 최소화가 되도록 연산의 순서를 수정한다. 벤치마크 프로그램에 대해 실험해 본 결과, 제안된 기법을 사용하여 명령어를 재배치하는 경우 명령어 추출시 스위칭 활동이 평균적으로 약 34%줄어듬을 확인하였다.

As mobile applications are required to handle more computing-intensive tasks, many mobile devices are designed using VLIW processors for high performance. In VLIW machines where a single instruction contains multiple operations, the power consumption during instruction fetches varies significantly depending on how the operations are arranged within the instruction. In this paper, we describe a post-pass optimal operation rearrangement method for low-power VLIW instruction fetch, The proposed method modifies operation placement orders within VLIW instructions so that the switching activity between successive instruction fetches is minimized. Our experiment shows that the switching activity can be 34% on average fro benchmark programs.

키워드

참고문헌

  1. A. Klaiber. The technology behind the Crusoe processor. Transmeta Corporation White Paper, 2000
  2. Fujitsu Microelectronics Inc. Fujitsu's new high performance VLIW processor cores. http://www.fujitsumicro.com/
  3. P. Faraboschi, G. Desoli, and J. A. Fisher. The latest word in digital and media processing. IEEE Signal Processing magazine, 15(2):59-85, 1998 https://doi.org/10.1109/79.664698
  4. R. Henning and C. Charkrabarti. High level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder. In Proc. of Int. Conf.on Computer Design (ICCD'97), pp. 571-576, 1997 https://doi.org/10.1109/ICCD.1997.628923
  5. Texas Instruments. TMS320 C600 Power Consumption Summary, 1999
  6. J. M. Puiatti, J. Llosa, C. Piguet, and E. Sanchez. Low Power VLIW Processors : A high level evaluation. In Proc. of Int. Workshop Power and Timing modeling Optimization and Simulation (PATMOS '98'), pp. 399-408, 1998
  7. A. Chandrakasan, T. Shung, and R. W. Broderson. Low Power CMOS digital design. IEEE Journal of Solid State Circuits, 27(4):473-484, 1992 https://doi.org/10.1109/4.126534
  8. S. Devadas and S. Malik. A survey of optimization techniques targeting low power VLSI Circits. In Proc. of Int.Symp.on Low Power Electronics and Design (ISLPED'97'), pp. 239-242, 1997
  9. M. R. Stan and W. P. Burleson. Bus invert coding for low power I/O. IEEE Trans. on VLSI Systems. 3(1):49-58, 1995 https://doi.org/10.1109/92.365453
  10. H. Mehta, R. M. Owens, M. J. Irwin, R. Chen, and D. Ghosh. Techniques for low energy software. In Proc. of Int. Symp. on Low Power Electronics and Design (ISLPED'97)', pp. 72-75, 1997 https://doi.org/10.1145/263272.263286
  11. C. L. Su, C. Y. Tsui, and A. Despain. Low power architechtural design and compilation technique for high performance prosessor. In Proc. of COMPCON94, pp. 489-498, 1994
  12. V. Tiwari, S. Malik, and A. Wolfe. Compilation techniques for low energy : An overview. In Proc. of Int. Symp. on Low Power Electronics, 1994 https://doi.org/10.1109/LPE.1994.573195
  13. V. Tiwari, S. Malik, and A. Wolfe. Power analysis of embedded software : A first step towards software power minimization. IEEE Trans. VLSI Systems, 2(4):437-445, 1994 https://doi.org/10.1109/92.335012
  14. M. T. Lee, V. Tiwari, S. Malik, and M. Fujita. Power analysis and minimization techniques for embedded DSP software. IEEE Trans. VLSi Systems, 5(1):123-135, 1997 https://doi.org/10.1109/92.555992
  15. H. Tomiyama, T. Ishihara, A. Inouc, and H. Yasuura. Instruction scheduling for power reduction in processor based system design. In Proc. of the 1998 Design Automation and Test in Europe(DATE '98'), pp. 855-860, 1998
  16. M. C. Toburen, T. M. Contc, and M. Reilly. Instruction scheduling for low power dissjpation in high performance microproccssors. In Proc. of Power Driven Microarchitecture Workshop, 1998
  17. C. Gebotys, R. Gebotys, and S. Wiratunga. Power minimization derived from architectural usage of VLIW processors. In Proc. of Conf. on Design Automation (DAC'2000), pp. 308-311, 2000
  18. T. Conte, S. Banerjia, S. Larin, K. N. Menezes, and S. W. Sathaye. Instruction fetch mechanisms for VLIW zrchitectures with compressed encodings. In Proc. of the 29th IEEE/ACM Int.Symp. on Microarchitecture, pp. 201-211, 1996
  19. Texas Instrumenets. TMS320C62xx CPU and Instruction Set, 1997
  20. E. Musoll, T. Lang, and L. Cortadella. Exploiting the locality of memory references to reduce the address bus energy. In Proc. of Int. Symp. on Low Power Electronics and Design (ISLPED'97'), pp. 202-207, 1997 https://doi.org/10.1145/263272.263334