대한전자공학회논문지SP (Journal of the Institute of Electronics Engineers of Korea SP)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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2차원 이산 웨이브렛 변환을 위한 효율적인 VLSI 구조

Efficient VLSI Architectures for the Two-Dimensional Discrete Wavelet Transform

  • 반성범 (서강대학교 전자공학과/한국전자통신연구원 멀티미디어연구부) ;
  • 박래홍 (서강대학교 전자공학과) ;
  • 지용 (서강대학교 전자공학과)
  • Pan, Sung-Bum (Dept. of Electronic Engineering, Sogang University/Electronics and Telecommunications Research Institute) ;
  • Park, Rae-Hong (Dept. of Electronic Engineering, Sogang University) ;
  • Jee, Yong (Dept. of Electronic Engineering, Sogang University)
  • 발행 : 2000.01.25
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 2차원 DWT 계산을 위한 효율적인 VLSI 구조를 제안한다 제안한 두 개의 구조는 $M{\times}N$ ($N{\times}M$) 블록 단위로 2 D DWT를 계산한다 각각의 블록에서 2 D DWT의 계산은 행 (열) 방향으로 동시에 계산한다 M은 필터 탭 수를 나타내고 N은 열 (행)을 나타낸다 그리고 행과 열 방향으로 1차원 DWT를 계산할 때 저주파와 고주파 성분을 하나의 구조에서 번갈아 계산하도록 하였다 그러므로 제안한 구조는 기존의 구조에 비해 부가적인 처리 유닛이 적게 필요하다 VHDL를 이용하여 모델링하고 시뮬레이션하여 제안한 구조가 정상적으로 동작함을 확인하였다.

This paper proposes efficient VLSI architectures for computation of the 2- D discrete wavelet transform (DWT). The two proposed VLSI architectures for the 2- D DWT are constructed based on block-based computation Each $M{\times}N$ ($N{\times}M$) block DWT is performed along the row (column) direction simultaneously, where M and N denote the number of filter taps and the number of columns (rows), respectively The proposed architectures compute the lowpass and highpass output sequences of the 1 - DWT along the row and column directions using a single architecture In alternate clock cycles Therefore the extra processing units required for the proposed architectures are much smaller than those of the conventional architectures They are modeled In very high speed Integrated circuit hardware description language (HIDL) and Simulated to show their functional validity.

키워드

참고문헌

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