한국정보과학회논문지:시스템및이론 (Journal of KIISE:Computer Systems and Theory)

한국정보과학회 (Korean Institute of Information Scientists and Engineers)
권호 표지

지연 제약 하에서 면적의 최적화를 위한 트랜지스터 사이징과 버퍼 삽입 알고리즘

Transistor Sizing and Buffer Insertion Algorithms for Optimum Area under Delay Constraint

  • 발행 : 2000.07.15
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⟨ 이전 논문 다음 논문 ⟩

초록

저 전력회로의 설계를 위해서, 전체 회로의 면적을 줄임으로써 용량성 부하(capacitance)값을 줄이는 방법으로 적절한 트랜지스터를 선택하여 사이징하는 방법을 이용할 수 있는데, 이 때 트랜지스터 사이징을 수행하면서 적당한 위치에 버퍼를 삽입하여주면 더 좋은 결과를 가져올 수 있다. 본 논문은 TILOS 알고리즘을 이용하여 트랜지스터 사이징(sizing)을 수행하는 동시에 버퍼의 삽입을 수행하는 알고리즘 두 가지를 소개하고 이 두 방법을 비교한다. 그 첫 번째 방법은 Template Window를 이용하여 직접 시뮬레이션하는 방법이고 다른 하나는 보외법(Extrapolation)을 이용하는 방법이다. 이와 같이 버퍼를 삽입하면서 트랜지스터 사이징을 수행한 결과, 버퍼를 삽입하지 않을 때 보다 10-20%의 면적감소를 얻었을 수 있었으며 보외법을 이용한 방법 보다 Template Window를 이용했을 때 더 좋은 결과를 얻을 수 있었다.

For designing circuits for low power systems, the capacitance is an important factor for the power dissipation. Since the capacitance of a gate is proportional to the area of the gate, we can reduce the total power consumption of a circuit by reducing the total area of gates, where total area is a simple sum of all gate areas in the circuit. To reduce the total area, transistor resizing can be used. While resizing transistors, inserting buffer in the proper position can help reduce the total area. In this paper we propose two methods for concurrent transistor sizing and buffer insertion. One method uses template window simulation and the other uses extrapolation. Experimental results show that concurrent transistor sizing with buffer insertion achieved 10-20% more reduction of the total area than when it was done without buffer insertion and template window simulation is more efficient than extrapolation.

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참고문헌

  1. Jose Monteiro and Srinvas Devadas, Computer-Aided Design Techniques For Low Power Sequential Logic Circuits, Kluwer Academic Publishers, 1997
  2. J. Fishburn and A. Dunlop, 'TILOS : A posynomial programming approach to transistorsizing,' in Proceeding of the IEEE International Conference on Computer-Aided Design, pp.326-328, 1985
  3. S. S. Sapatnekar, V. B. Rao, P. M. Vaildya, and S. M. Kang, 'An exact solution to the transistor sizing problem for CMOS circuits using convex optimization,' IEEE Transactions on Computer-Aided Design, vol. 12, pp. 1621-1634, Nov. 1993 https://doi.org/10.1109/43.248073
  4. M. Borah, R. M. Owens, and M. J. Irwin, 'Transistor sizing for low power CMOS circuits,' IEEE Transactions on Computer-Aided Design. vol. 15. pp 665-671, June 1996 https://doi.org/10.1109/43.503935
  5. K. J. Singh and A. Samgiovanni-Vincentelli, 'A heuristic algorithm for the fanout problem,' in Proceedings of the ACM/IEEE Design Automation Conference, pp. 357-360, 1988 https://doi.org/10.1109/DAC.1990.114882
  6. C. L. Berman, J. I,. Carter, and K. L. Day, 'The fanout problem : From theory to practice,' in Advanced Research in VLSI: Proceedings of the 1989 Decennial Caltech Conference, pp. 69-99, 1989
  7. Yanbin Jiang, Sachin Sapatnekar, Cyrus Bamji and Juho Kim, 'Interleaving Buffer Insertion and Transistor Sizing into a Single Optimization,' IEEE Transactions VLSI systems. pp625-633, 1998 https://doi.org/10.1109/92.736136
  8. A. Raiston and P. Ravinowitz, A First Course in Numerical Analysis. New York: McGraw-Hill, 1978
  9. Juho Kim, Cyrus Bamji, Yanbin Jiang and Sachin Sapatnekar, 'Concurrent Transistor Sizing and Buffer Insertion by Considering Cost-Delay Tradeoffs,' Proceedings of 1997 International Symposium on Physical Design, pp. 130-135 https://doi.org/10.1145/267665.267703
  10. J. Rubinstein, P. Penfield, and M. A. Horowitz, 'Signal delayin RC tree networks,' IEEE Transactions on Computer-Aided Design, vol. CAD-2, pp. 202-211, July 1983
  11. W. C. Elmore. 'The Transient Response of Damped Linear Networks with Particular Regardto Wideband Amplifiers,' Journal of Applied Physic, vol 19(1), pp. 55-63, 1948 https://doi.org/10.1063/1.1697872
  12. C. L. Fang and W. B. Jone, 'Timing Optimization by Gate Resizing and Critical Path Identification,' IEEE Transactions on Computer Aided Design, Vol.14, No 2, pp.201-217, February 1995 https://doi.org/10.1109/43.370424
  13. J. Kim, Y. Hsu, and D. Du, 'A New Gate Selection Method for Resizing to Circuit Performance Optimization,' in Proc. ISCAS, Vol. 4, pp.461-464, May 1996 https://doi.org/10.1109/ISCAS.1996.542001
  14. M. Borah, R. M. Owens, and M. J. Irwin, 'Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint,' in Proc. Int'l Symp. on Low PowerDesign, pp.167-172, April 1995 https://doi.org/10.1145/224081.224111
  15. M. Sarrafzadeh and D. S. Chen, 'An Exact Algorithm for Low Power Library-Specific Gate Resizing,' in Proc. 33rd Design Automation Conference, pp.783-788,June 1996 https://doi.org/10.1145/240518.240666
  16. P. Girard, C. Landrault, S. Pravossoudovich, and D. Severac, 'A Gate Resizig Technique for High Reduction in Power Consumption,' in Proc. Int'l Symp. on Low Power Design, pp.281-286, August 1997 https://doi.org/10.1145/263272.263352
  17. C. H. Tan and J. Allen, 'Minimiztion of Power in VLSI Circuits Using Transistor Sizing, Input Ordering, and Statistical Power Estimation,' in Proc. Int'l Symp. on Low Power Design, pp.75-80, August 1994