Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A New Accurate Interconnect Delay Model and Its Experiment Verification

연결선에 기인한 시간지연의 정확한 모델 및 실험적 검증

  • Yoon, Seong-Tae (Dept. of Electronic Engineering, Hanyang University) ;
  • Eo, Yung-Seon (Dept. of Electronic Engineering, Hanyang University) ;
  • Shim, Jong-In (Dept. of Electronic Engineering, Hanyang University)
  • Published : 2000.09.01
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Abstract

A new analytical VLSI interconnect delay model is presented and its accuracy is experimentally verified. In the model, the transmission line parameter variations due to skin effect, proximity effect, and silicon substrate effect are taken into account. That is, the circuit model of the interconnect line that includes these effects is newly developed and analyzed. For the model verification, test patterns combined the coplanar structure with microstrip were designed by using 0.35${\mu}m$ CMOS process technology. It is shown that the accuracy of the model is less than about 10% error.

본 논문에서는 고속 VLSI 회로 내의 전송선에서 발생하는 전달지연시간을 계산하는 해석적 모델을 제시하고 그 모델의 정확성을 실험적으로 검증한다. 새로 제시한 모델은 표피효과, 근접효과 그리고 실리콘 기판에 의한 전성선 파라미터 변화를 고려하기 때문에 이들 영향을 반영한 새로운 인터커넥트 회로모델에 대하여 시간지연 모델을 구현한다. 모델의 정확성을 검증하기 위해 코플레너(coplanar)와 마이크로 스트립구조가 결합한 패턴의 모델을 0.35${\mu}m$ CMOS 공정을 사용하여 제작하였다. 이들 테스트 패턴에 대한 실험적 검증을 통하여 모델이 약 10% 이내의 오차범위에서 정확하다는 것을 보인다.

Keywords

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