BILI-하드웨어/소프트웨어 분할 휴리스틱

BILI-Hardware/Software Partition Heuristic

  • 오현옥 (서울大學校 電氣 및 컴퓨터工學部) ;
  • 하순회 (서울大學校 電氣 및 컴퓨터工學部)
  • Oh Hyun-Ok (School of Electrical Engineering & Computer Science, Seoul National University) ;
  • Ha, Soon-Hoi (School of Electrical Engineering & Computer Science, Seoul National University)
  • 발행 : 2000.09.01

초록

이 논문에서는 Best Imaginary Level-Iterative(BILI) 분할 방법이라 부르는 새로운 하드웨어/소프트웨어 분할 알고리즘을 제안하다. 이 분할 알고리즘은 여러 개의 하드웨어와 소프트웨어로 이루어진 시스템에 대해서 분할을 할 수 있을 뿐만 아니라, 여러 가지의 구현 가능성 중에서 적은 비용의 구현을 선택하는 문제까지 해결한다. 이 분할 알고리즘은 기존의 분할 알고리즘인 GCLP와 비교하여 약 15%의 비용 감소를 가지고, 항상 최적의 해를 찾는 장수 선형 프로그래밍과 비교하여 약 5%정도의 비용 증가를 가진다.

This paper presents a fast partitioning heuristic for hardware/software codesign called Best Imaginary Level-Iterative(BILI) partitioning which iteratively applies BIL heterogeneous multiprocessor scheduling heuristic to minimize the cost within the given time constraint. The proposed algorithm solves the partitioning problem with the implementation bin selection problem as well as architectures with multiple software modules. It costs about 15% less than the GCLP and at most about 5% more than the optimal solution obtained by the Integer Linear Programming(ILP) algorithm.

키워드

참고문헌

  1. S. Edwards, L. Lavagno, E. A. Lee and A. Sangiovanni-Vincentelli, 'Design of Embedded Systems: Formal Models, Validation, and Synthesis.' in Proceedings of IEEE. vol. 85. no. 3. pp 366-390. Mar. 1997 https://doi.org/10.1109/5.558710
  2. 오현옥, 하순회, '이종 프로세서를 위한 정적인 스케줄링 휴리스틱.' 정보과학회논문지(A) 제25권 제12호 1339-1347. 1998년 12월 Hyunok Oh and Soonhoi Ha , 'A Static Scheduling Heuristic for Heterogeneous processors.' Second International Euro-Par Conference Proceedings, Volume II, Lyon, France, August 1996
  3. Hyunok Oh and Soonhoi Ha , 'A Static Scheduling Heuristic for Heterogeneous processors.' Second International Euro-Par Conference Proceedings, Volume II, Lyon, France, August 1996
  4. J. Henkel, R. Ernst, U. Holtmann and T. Benner, 'Adaptation of partitioning and high-level synthesis in hardware/software cosynthesis.' in Proc. Int. Conf. on Computer-Aided Design. Nov. 1994
  5. S. Kumar, J. H. Aylor, B. W. Johnson and W. A. Wulf, ' Exploring hardware/software abstractions and alternatives for codesign.' in Proc. Int. Workshop on Hardware-Software Codesign. Oct. 1993
  6. X. Hu, J. G. D'Ambrosio, B. T. Murray, and D.-L. Tang, 'Codesign of architectures for powertrain modules.' IEEE Micro, vol. 14, no. 4, pp. 48-58, Aug. 1994 https://doi.org/10.1109/40.296154
  7. R Nieman and P. Marwedel, 'An Algorithm for Hardware/Software Partitioning Using Mixed Integer Linear Programming.' Design Automation for Embedded Systems, special Issue : Partitioning Methods for Embedded Systems. Vol. 2, No.2, 165-193, Kluwer Academic Publishers, March 1997 https://doi.org/10.1023/A:1008832202436
  8. R.K. Gupta, C. Coelho, and G. De Micheli, 'Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components.' 29th ACM, IEEE Design Automation Conference, pages 225-230, 1992
  9. R.K. Gupta, C. Coelho, and G. De Micheli, 'Program implementation schemes for hardware-software systems.' IEEE Computer, pp.48-55, Jan. 1994 https://doi.org/10.1109/2.248880
  10. K. Olokuntun, R. Helaihel, J. Levitt and R. Ramirez, 'A software-hardware cosynthesis approach to digital system simulation.' IEEE Micro, vol. 14, no. 4, pp. 48-58, Aug. 1994 https://doi.org/10.1109/40.296157
  11. F. Vahid and T. D. Le, 'Extending the Kernghan/Lin Heuristic for Hardware and Software Functional Partitioning.' Design Automation for Embedded Systems, special Issue: Partitioning Methods for Embedded Systems. Vol. 2, No.2, 237-261, Kluwer Academic Publishers, March 1997
  12. A. Kalavade and E.A. Lee, 'A Global Critically/Local Phase Driven Algorithm for the Constrained Hardware/Software Partitioning Problem.' Third International Workshop on Hardware/Software Codesign, Grenoble, pages 42-48, 1994
  13. A. Kalavade and E.A. Lee, 'The Extended Partitioning Problem: Hardware/Software Mapping and Implementation-Bin Selection.' Proceedings of the 6th International Workshop on Rapid Systems Prototyping, 1995 https://doi.org/10.1109/IWRSP.1995.518565
  14. Hamada, T.Banerjee, S.Chau, P.M. Fellman, R.D, 'Macropipelining based heterogeneous multiprocessor scheduling', Proceedings of ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech and Signal Processing, San Francisco, CA, USA, 23-26 March 1992, New York, NY, USA: IEEE, 1992, p.597- 600 vol. 5 https://doi.org/10.1109/ICASSP.1992.226549
  15. G.C Sih and E. A. Lee, 'A Compile-Time Scheduling Heuristic for lnterconnection-Constrained Heterogeneous Processor Architectures', IEEE Trans. parallel and distributed systems, vol 4, no.2, pp. 175-187, Feb. 1993 https://doi.org/10.1109/71.207593
  16. http://peace.snu.ac.kr/