대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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멀티미디어 통신용 병렬 아키텍쳐 고속 비터비 복호기 설계

Implementation of a Parallel Viterbi Decoder for High Speed Multimedia Communications

  • 발행 : 2000.02.01
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⟨ 이전 논문 다음 논문 ⟩

초록

비터비 복호기는 직렬 복호 방식과 병렬 복호 방식 2 가지로 분류할 수 있다. 병렬 비터비 복호기는 직렬비터비 복호기에 비해 보다 높은 데이타율을 얻을 수 있다. 본 논문에서는 고속 멀티미디어 통신을 위한 병렬 비티비 복호기 구조를 설계하고 구현한다. 설계한 비터비 복호기는 고속 동작을 위해 64개의PE(Processing Element)를 사용해 한 클럭에 처리가 가능하도록 하였다. 또한 파이프라인 스테이지를 갖는 시스톨릭 어레이 구조의 TB(Traceback) 블럭을 설계하였다. 본 논문에서 설계한 비터비 복호기는 puncturing을 통해 부호율 1/2, 2/3, 3/4, 5/6, 7/8을 지원한다. Verilog 모델을 구현하였고 0.6㎛ Samsung KG75000 SOG 셀 라이브러리를 이용하여 논리합성을 수행하였다. 구현된 비터비 복호기는 약100,400 게이트이며 동작 속도는 worst case에서 70㎒로 기존 상용 칩들보다 빠르다.

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

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