References
- Proc. IEEE International Test Conference DFT Strategy For Intel Microprocessors Wayne Needham;Nags Gollakota
-
Proc. IEEE International Test Conference
Testability Features Of The Super
$SPARC^ {TM}$ Microprocessor Rajiv Patel;Krishna Yarlagadda -
Proc. IEEE International Test Conference
Structured Design for Debug the Super
$SPARC^ {TM}$ II Methodology and Implementation Hong Hao;Rick Avra - IEEE Std 1149-1-1990(including IEEE Std,1149.1a-1993) IEEE Standard Test Access Port and Boundary-Scan Architecture
- IEEE Standard Test Access Port and Boundary Scan Architecture Test Technology Standards Committee
- Boundary-Scan Test H.Bleeker;P.ven den Eijnden;F.de Jong
- Logic Testing and Design for Teatability H.Fujiwara
- Int. Proc. Symp On Mathemaical Theory of Automata Derivation of Optimum tests to detect faults in combinational circuits E.Poage
- Testing Semiconductor Memories: Theory and Practice A.J.Goor
- Proc. IEEE Internaional Test Conference A Realistic Self-Test Machine for Static Random Access Memories R.Dekker;F.Beenker;L.Thijseen
- Testing and Testable Design of High-Density Random-Access Memories Pinamik Mazumder;Kanad Chakraborty