The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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An Efficient Kernel-based Partitioning Algorithm for Low-power Low-Power Low-area Logic Circuit Design

저전력 저면적의 논리 회로 설계를 위한 효율적인 커널 기반 분할 알고리듬

  • 황선영 (서강대학교 전자공학과) ;
  • 김형 (경민대학 소프트웨어개발과) ;
  • 최익성 (한국전자통신연구원 교환전송기술연구소) ;
  • 정기조 (서강대학교 전자공학과)
  • Published : 2000.08.01
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Abstract

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.

본 논문에서는 조합 논리 회로의 면적과 전력 소모를 낮추기 위한 효율적인 커널 기반의 분할 알고리듬을 제안 한다. 제안한 알고리듬은 커널을 이용하여 회로를 분할함으로써 회로의 전력 소모를 줄이고 분할된 회로들의 중복 되는 게이트를 최소화시켜 면적 overhead를 감소시킨다. MCNC 표준 테스트 회로에 대한 실험을 통하여 제안된 알고리듬이 면적과 전력소모면에 있어서 기존의 precomputation 회로 구조에 바탕을 둔 알고리듬에 비해 전력 소모는 평균 43.6% 면적은 평균30.7% 향상된 결과를 보인다.

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References

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