한국통신학회논문지 (The Journal of Korean Institute of Communications and Information Sciences)

  • 제25권9A호
  • /
  • Pages.1332-1339
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  • 2000
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  • 1226-4717(pISSN)
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  • 2287-3880(eISSN)
한국통신학회 (The Korean Institute of Commucations and Information Sciences)
권호 표지

CATV 망용 고속 비대칭 기저대역 모뎀 ASIC 칩 설계

Design of a High Speed Asymmetric Baseband MODEM ASIC Chip for CATV Network

  • 발행 : 2000.09.01
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 MCNS(Multimedia Cable N$\xi$twork System)의 DOCSIS(Data Over Cable Service Interface S Specification) 표준안의 물리계층을 지원하는 비대칭형 기저대역 모댐 ASIC 칩의 아키텍쳐와 설계에 대해 기술한다. 구현한 모뎀 칩은 크게 QPSK/16-QAM 방식의 상향 스트림용 송신부와 64/256-QAM 방식의 하향 스트림용 수신부로 구성되어 있으며, 심볼 타이밍 복구회로, 반송파 복구회로. MMA(Multi Modulus Algorithm)와 LMS(Least Mean Square) 알고리즘을 적용한 결정 궤환 구조의 블라인드 등화기를 포함한다. 구현한 모뎀 칩은 64/256-QAM 변복조 방식에서 각각 48Mbps, 64Mbps의 데이터 전송률을 지원하고, 심볼 전송률은 기존의 QAM 수신기들보다 빠른 8MBaud를 갖는다. 구현한 칩은 $0.35\mu\textrm{m}$ 표준 셀(Standard Cell) 라이브러리를 사용하여 논리합성을 수행하였으며, 총 게이트 수는 약 29만 게이트이며, 현재 ASIC 칩으후 제작중이다.

This paper presents the architecture and design of a high speed asymmetric data transmission baseband MODEM ASIC chip for CATV networks. The implemented MODEM chip supports the physical layer of the DOCSIS(Data Over Cable Service Interface Specification) standard in MCNS(Multimedia Cable Network System) The chip consists of a QPSK/16-QAM transmitter and a 64/256-QAM receiver which contain a symbol timing recovery circuit, a carrier recovery circuit, a blind equalizer using MMA and LMS algorithms. The chip can support data rates of 64Mbps at 256 QAM and 48Mbps at 64-QAM and can provide symbol rates up to 8MBaud. This symbol rate is faster than existing QAM receivers. We have performed logic synthesis using the $0.35\mu\textrm{m}$ standard cell library. The total number of gates is about 290,000 and the implemented chip is being fabricated and will be delivered soon.

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참고문헌

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