The Analysis of Characteristics on n-channel Offset-gated poly-Si TFT's with Electical Stress

전기적 스트레스에 따른 Offset 구조를 갖는 n-채널 다결정 실리콘 박막 트랜지스터의 특성 분석

  • 변문기 (수원대학교 전자재료공학과) ;
  • 이제혁 (수원대학교 전자재료공학과) ;
  • 임동규 (수원대학교 전자재료공학과) ;
  • 백희원 (수원대학교 전자재료공학과) ;
  • 김영호 (수원대학교 전자재료공학과)
  • Published : 2000.02.01

Abstract

The effects of electrical on n-channel offset gated poly-Si TFT's have been investigated. It is observed that the electrical field near the drain region in offset devices is smaller than that of conventional device by simulation results. The variation rate of threshold voltage and subthreshold slope decrease with increasing the offset length because of lowering the electric field near the drain region. The offset gated poly-Si TFT's have been probed effective in reducing the degradation rate of device performance under electrical stressing.

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References

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