대한전기학회논문지:시스템및제어부문D (The Transactions of the Korean Institute of Electrical Engineers D)

대한전기학회 (The Korean Institute of Electrical Engineers)
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MBDD를 이용한 저전력 VLSI설계기법

A Method of Low Power VLSI Design using Modified Binary Dicision Diagram

  • 발행 : 2000.06.01
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초록

In this paper, we proposed MBDD(Modified Binary Decision Diagram) as a multi-level logic synthesis method and a vertex of MBDD to NMOS transistors matching. A vertex in MBDD is matched to a set of NMOS transistors. MBDD structure can be achieved through transformation steps from BDD structure. MBDD can represent the same function with less vertices less number of NMOS transistors, consequently capacitance of the circuit can be reduced. Thus the power dissipation can be reduced. We applied MBDD to a full odder and a 4-2compressor. Comparing the 4-2compressor block with other synthesis logic, 31.2% reduction and 19.9% reduction was achieved in numbers of transistors and power dissipation respectively. In this simulation we used 0.8 ${\mu}{\textrm}{m}$ fabrication parameters.

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참고문헌

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