전자통신동향분석 (Electronics and Telecommunications Trends)
- 제13권5호통권53호
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- Pages.11-22
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- 1998
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- 1225-6455(pISSN)
DOI QR Code
NUMA 다중 프로세서에서의 캐쉬 일관성 프로토콜
Cache Coherence Protocols in NUMA Multiprocessors
- Moh, Sang-Man (Computer System Department) ;
- Hahn, Woo-Jong (Computer System Department) ;
- Yoon, Suk-Han (Computer System Department)
- 발행 : 1998.08.15
초록
Recently, scalable multiprocessor systems are actively developed for general-purpose computing, which are based on distributed shared memory (DSM) architecture to boost up both programmability and scalability. In this paper, we survey and analyze cache coherence protocols in non-uniform memory access (NUMA) multiprocessor systems. In particular, it has been easily inferred that specialized hardware suitable for NUMA multiprocessor systems with commodity symmetric multiprocessors (SMPs) is highly required. The cache coherence protocol combined with specialized hardware can significantly improve the performance and scalability of NUMA multiprocessor systems, providing better programmability.
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