Journal of the Korean Institute of Telematics and Electronics S (전자공학회논문지S)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design and Fabrication of 10Gb/s FPLL Clock and Data Regeneration Circuit

10Gb/s FPLL 방식 클럭/데이터 재생회로 설계 및 제작

  • Song, Jae-Ho (Transmission Technology Department Electronics and Telecommunications Research Institute) ;
  • Yoo, Tae-Hwan (Transmission Technology Department Electronics and Telecommunications Research Institute) ;
  • Park, Chang-Soo (Transmission Technology Department Electronics and Telecommunications Research Institute)
  • 송재호 (韓國電子通信硏究院 광대역전송연구부) ;
  • 유태환 (韓國電子通信硏究院 광대역전송연구부) ;
  • 박창수 (韓國電子通信硏究院 광대역전송연구부)
  • Published : 1998.12.01
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Abstract

in this work, we designed and characterized a 10Gb/s clock and regeneration circuit. The circuit was realized by integrating high-speed ICs and microwave circuits on alumina substrates. The quadri-correlation method was used for frequency and phase-locked loop. The frequency locking range was 150MHz and the rms jitter generated by the circuit was measured to be less than 1.0ps. The clock and data regeneration circuit was successfully applied to 10Gb/s optical receiver.

본 논문에서는 10Gb/s 클럭/데이터 재생회로의 설계와 제작된 특성에 대해 기술한다. 회로는 알루미나 기판 위에 고속 IC와 초고주파 회로를 이용하여 구현하였다. 주파수와 위상 잠금(frequency and phase locked loop)을 위해 quadri-correlation 방법을 이용하였다. 주파수 잠금 범위는 150MHz 였으며 발생된 rms 지터는 1.0ps 이하였다. 이러한 클럭/데이터 재생회로를 10Gb/s광수신기에 적용하여 동작특성을 확인할 수 있었다.

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