A Study of Synthesis Algorithm for Component Mapping

콤포넌트 맵핑을 위한 합성 알고리즘에 관한 연구

In this paper proposed Component Synthesis Algorithm(CSA) for mapping described HDL to RT component of given library. CSA transform I/O variables of HDL and relation of operators to control/data flow graph(CDFG) that consists of graph, reduce the size of graph, compute the cost, the bound, and the method that use compatibility graph(CG), and then mapping to component. Component synthesis used branch-and-bound algorithm. The result that synthesis using CSA algorithm was proved that this result and the cost of the manual were indentified.

본 는문에서는 RT콤포넌트를 이용한 맵핑 방법으로 HDL로 기술된 연산자들을 RT콤포넌트에 맞도록 CDFG를 구성한 후 그래프를 최소화하고 cost와 bound를 계산하여 적합한 라이브러리를 선정하여 맵핑할 수 있는 콤포넌트 합성 알고리즘(Component Synthesis Algorithm)을 제안하였다.