The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Search space pruning technique for optimization of decision diagrams

결정 다이어그램의 최적화를 위한 탐색공간 축소 기법

  • 송문배 (숭실대학교 대학원 전자계산학과) ;
  • 동균탁 (숭실대학교 대학원 전자계산학과) ;
  • 장훈 (숭실대학교 컴퓨터학부)
  • Published : 1998.08.01
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Abstract

The optimization problem of BDDs plays an improtant role in the area of logic synthesis and formal verification. Since the variable ordering has great impacts on the size and form of BDD, finding a good variable order is very important problem. In this paper, a new variable ordering scheme called incremental optimization algorithm is presented. The proposed algorithm reduces search space more than a half of that of the conventional sifting algorithm, and computing time has been greatly reduced withoug depreciating the performance. Moreover, the incremental optimization algorithm is very simple than other variable reordering algorithms including the sifting algorithm. The proposed algorithm has been implemented and the efficiency has been show using may benchmark circuits.

BOD의 최적화 문제는 논리합성과 형식검증 영역에서 필수적인 것으로 인식되고 있다. 변수 순서화 문제는 BOD의 크기와 형태에 직접적인 영향을 미치므로, 적절한 변수 순서를 구하는 문제는 매우 중요한 문제이다, 본 논문에서 는 점진적 시프팅이라 부르는 새로운 변수 순서화 알고리듬을 소개한다. 제안된 알고리듬은 기존의 시프팅 알고리듬에서의 탐색공간을 절반이하로 줄이며, 성능의 저하없이 계산시간을 크게 감소시킬 수 있다. 더욱이 점진적 시프팅 알고리듬은 시프팅 알고리듬을 비롯한 다른 변수 순서화 알고리듬에 비해 매우 단순하다. 제안된 알고리듬은 많은 벤치마크 회로를 이용한 실험에서 그 효율성이 입증되었다.

Keywords

References

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